Galvanically isolated data isolator with improved common mode transient rejection

• US 10,205,442 B2
• Filed: 08/08/2016
• Issued: 02/12/2019
• Est. Priority Date: 08/08/2016
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Lynch, Michael, Moane, Brian Anthony
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/230,519
• Publication Number:
  US 20180041200A1
• Time in Patent Office: 918 Days
• Field of Search: None
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H03K 17/56 by the use, as active elements, of semiconductor devices using diodes H03K17/74
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A transformer based digital isolator is provided that has improved immunity to common mode interference. The improved immunity is provided by placing the transformer in association with an H-bridge drive circuit, and taking additional effort to tailor the on state resistance of the transistors to control a common mode voltage at the transformer.

Claims

1. A data isolator comprising:

a transformer including a primary winding and a secondary winding, the primary winding having first and second connections to an H-bridge circuit comprising a plurality of transistors; and

wherein the primary winding of the transformer is connected to the H-bridge circuit without a DC blocking component, the H-bridge circuit is configured to control a current flow in the primary winding of the transformer, and the plurality of transistors have on-state resistances such that a voltage at a midpoint of the primary winding is substantially at a common mode voltage of the H-bridge circuit.

2. The data isolator as claimed in claim 1, wherein the H-bridge circuit is configured to provide an encoded signal to the primary winding of the transformer to induce a signal in the secondary winding of the transformer and wherein the data isolator further comprises a receiver to reconstruct a data signal based on the signal induced in the secondary winding of the transformer.

3. The data isolator as claimed in claim 2, wherein the signal induced in the secondary winding of the transformer comprises monophasic pulses.

4. The data isolator as claimed in claim 2, wherein the receiver is configured to reconstruct the data signal at least in part by detecting a voltage difference between first and second nodes of the secondary winding.

5. The data isolator as claimed in claim 4, wherein a sign of the voltage difference is indicative of a direction of current flow or change of direction of current flow in the primary winding of the transformer.

6. The data isolator as claimed in claim 1, wherein the plurality of transistors includes first and second P-type transistors and first and second N-type transistors.

7. The data isolator as claimed in claim 6, wherein the on-state resistance of the plurality of transistors is matched and wherein the first and second P-type transistors have different doping concentrations than the first and second N-type transistors.

8. The data isolator as claimed in claim 6, wherein the on-state resistance of the plurality of transistors is matched and wherein the first and second P-type transistors have a different size than the first and second N-type transistors.

9. The data isolator as claimed in claim 6, further comprising a resistance coupled in series with one or more of the plurality of transistors such that the on-state resistance of the plurality of transistors is matched.

10. The data isolator as claimed in claim 2, wherein the encoded signal comprises a first sequence of pulses representative of a rising edge in the data signal and a second sequence of pulses representative of a falling edge in the data signal that is different from the first sequence of pulses.

11. The data isolator as claimed in claim 6, wherein the first and second P-type transistors have an aspect ratio that differs from the aspect ratio of the first and second N-type transistors by more than a factor of 2.

12. The data isolator as claimed in claim 11, wherein the first and second P-type transistors have an aspect ratio that differs from the aspect ratio of the first and second N-type transistors by more than a factor of 3.

13. The data isolator as claimed in claim 11, wherein the first and second P-type transistors have an aspect ratio that differs from the aspect ratio of the first and second N-type transistors by more than a factor of 3.5.

14. The data isolator as claimed in claim 1, wherein the transformer is a micro transformer.

15. The data isolator as claimed in claim 1, wherein the data isolator is provided in a chip scale package.

16. An isolator comprising:

a transformer including a primary winding configured to be driven by a H-bridge circuit, wherein the H-bridge circuit comprises a plurality of controllable current paths, and an on-state resistance of each current flow path in the plurality of controllable current paths is matched to an associated current flow path in the plurality of controllable current paths.

17. The isolator as claimed in claim 16, wherein the on-state resistances are matched such that voltage changes at first and second nodes of the primary winding caused by a common mode voltage change are substantially equal.

18. The isolator as claimed in claim 16, wherein the transformer is a micro transformer and the isolator is provided in a chip scale package.

19. A method of operating an isolator comprising a transformer, the method comprising:

driving a primary winding of the transformer by a H-bridge circuit, where the on-state impedance at first and second connections to the primary winding are substantially matched.

20. The method as claimed in claim 19, wherein the transformer is DC coupled to the H-bridge circuit.

21. A data isolator comprising:

a micro transformer including a primary winding and a secondary winding, the primary winding having first and second connections to an H-bridge circuit; and

wherein the primary winding of the micro transformer is connected to the H-bridge circuit without a DC blocking component and the H-bridge circuit is configured to control a current flow in the primary winding of the micro transformer.

22. The data isolator as claimed in claim 21, wherein the H-bridge circuit is configured to provide an encoded signal to the primary winding of the micro transformer to induce a signal in the secondary winding of the micro transformer and wherein the data isolator further comprises a receiver to reconstruct a data signal based on the signal induced in the secondary winding of the micro transformer.

23. The data isolator as claimed in claim 22, wherein the encoded signal comprises a first sequence of pulses representative of a rising edge in the data signal and a second sequence of pulses representative of a falling edge in the data signal that is different from the first sequence of pulses.

24. The data isolator as claimed in claim 22, wherein the signal induced in the secondary winding of the micro transformer comprises monophasic pulses.

25. The data isolator as claimed in claim 22, wherein the receiver is configured to reconstruct the data signal at least in part by detecting a voltage difference between first and second nodes of the secondary winding.

26. The data isolator as claimed in claim 25, wherein a sign of the voltage difference is indicative of a direction of current flow or change of direction of current flow in the primary winding of the micro transformer.

27. The data isolator as claimed in claim 21, wherein the data isolator is provided in a chip scale package.