Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

• US 10,205,461 B2
• Filed: 09/29/2017
• Issued: 02/12/2019
• Est. Priority Date: 03/03/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Aleksic, Marko, Leibowitz, Brian S.
• Primary Examiner(s): Le, Toan K
• Application Number:
  US15/720,401
• Publication Number:
  US 20180198455A1
• Time in Patent Office: 501 Days
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Claims

1. A circuit, comprising:

a first injection-locked oscillator (ILO) to generate a first output signal based on an input signal, wherein the first ILO has a first free-running frequency that is capable of being adjusted based on a first control signal;

a second ILO to generate a second output signal based on the input signal, wherein the second ILO has a second free-running frequency that is capable of being adjusted based on a second control signal; and

circuitry to generate the first control signal and the second control signal.

2. The circuit of claim 1, wherein the circuitry to generate the first control signal and the second control signal sweeps the first free-running frequency of the first ILO and the second free-running frequency of the second ILO in opposite directions.

3. The circuit of claim 1, wherein the circuit comprises circuitry to detect a phase boundary between two adjacent phase tuning ranges of the first ILO or the second ILO.

4. The circuit of claim 3, wherein the circuitry to detect the phase boundary comprises a first demultiplexer to inject the input signal into one or more injection points of the first ILO, wherein each injection point in the first ILO corresponds to a phase tuning range of the first ILO.

5. The circuit of claim 4, wherein the circuitry to detect the phase boundary comprises a second demultiplexer to inject the input signal into one or more injection points of a second ILO, wherein each injection point in the second ILO corresponds to a phase tuning range of the second ILO.

6. The circuit of claim 3, wherein the circuitry to detect the phase boundary comprises circuitry to determine a phase difference between the first output signal and the second output signal.

7. The circuit of claim 3, wherein the circuitry to detect the phase boundary comprises circuitry to switch between adjacent phase tuning ranges in response to determining that a phase difference between the first output signal and the second output signal is substantially equal to a pre-determined value.

8. A memory system, comprising:

a memory device; and

a memory controller that orchestrates data flow to and from the memory device, the memory controller comprising;

a first injection-locked oscillator (ILO) to generate a first output signal based on an input signal, wherein the first ILO has a first free-running frequency that is capable of being adjusted based on a first control signal;

a second ILO to generate a second output signal based on the input signal, wherein the second ILO has a second free-running frequency that is capable of being adjusted based on a second control signal; and

circuitry to generate the first control signal and the second control signal.

9. The memory system of claim 8, wherein the circuitry to generate the first control signal and the second control signal sweeps the first free-running frequency of the first ILO and the second free-running frequency of the second ILO in opposite directions.

10. The memory system of claim 8, wherein the circuit comprises circuitry to detect a phase boundary between two adjacent phase tuning ranges of the first ILO or the second ILO.

11. The memory system of claim 10, wherein the circuitry to detect the phase boundary comprises a first demultiplexer to inject the input signal into one or more injection points of the first ILO, wherein each injection point in the first ILO corresponds to a phase tuning range of the first ILO.

12. The memory system of claim 11, wherein the circuitry to detect the phase boundary comprises a second demultiplexer to inject the input signal into one or more injection points of a second ILO, wherein each injection point in the second ILO corresponds to a phase tuning range of the second ILO.

13. The memory system of claim 10, wherein the circuitry to detect the phase boundary comprises circuitry to determine a phase difference between the first output signal and the second output signal.

14. The memory system of claim 10, wherein the circuitry to detect the phase boundary comprises circuitry to switch between adjacent phase tuning ranges in response to determining that a phase difference between the first output signal and the second output signal is substantially equal to a pre-determined value.

15. A method, comprising:

generating, by using a first injection-locked oscillator (ILO), a first output signal based on an input signal, wherein the first ILO has a first free-running frequency that is capable of being adjusted based on a first control signal;

generating, by using a second ILO, a second output signal based on the input signal, wherein the second ILO has a second free-running frequency that is capable of being adjusted based on a second control signal; and

generating the first control signal and the second control signal.

16. The method of claim 15, comprising using the first control signal and the second control signal to sweep the first free-running frequency of the first ILO and the second free-running frequency of the second ILO in opposite directions.

17. The method of claim 15, comprising detecting a phase boundary between two adjacent phase tuning ranges of the first ILO or the second ILO.

18. The method of claim 17, wherein said detecting the phase boundary comprises injecting the input signal into one or more injection points of the first ILO, wherein each injection point in the first ILO corresponds to a phase tuning range of the first ILO.

19. The method of claim 18, wherein said detecting the phase boundary comprises injecting the input signal into one or more injection points of a second ILO, wherein each injection point in the second ILO corresponds to a phase tuning range of the second ILO.

20. The method of claim 17, wherein said detecting the phase boundary comprises determining a phase difference between the first output signal and the second output signal.