Apparatus for overload recovery of an integrator in a sigma-delta modulator

• US 10,205,465 B2
• Filed: 04/21/2017
• Issued: 02/12/2019
• Est. Priority Date: 06/25/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Kauffman, John G., Dufrene, Krzysztof
• Primary Examiner(s): Lauture, Joseph
• Application Number:
  US15/494,408
• Publication Number:
  US 20170288692A1
• Time in Patent Office: 662 Days
• Field of Search: 341118, 341120, 341155, 341156, 341143
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/06 Continuously compensating for, or preventing, undesired influence of physical parameters periodically, e.g. by using stored correction values, H03M1/10
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/10 Calibration or testing
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H03M 3/356 Offset or drift compensation removal of offset already present on the analogue input signal H03M3/494
• CPC Class Codes: H03M 3/386 over the full range of the converter, e.g. for correcting differential non-linearity
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/444 using non-linear elements, e.g. limiters
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path

Abstract

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

Claims

1. An apparatus comprising:

an amplifier having an input and an output;

a capacitor coupled to the input and the output of the amplifier;

an analog-to-digital converter (ADC) coupled to the output of the amplifier;

a Digital-to-Analog converter (DAC) coupled to an output of the ADC and to the input of the amplifier; and

a circuitry coupled to the output of the ADC and the output of the DAC, wherein the circuitry is to compensate for an excess delay of at least a portion of a feedback path comprising the ADC, wherein the DAC comprises;

a p type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.

2. The apparatus of claim 1, wherein the circuitry is to compensate the excess delay associated with the ADC and DAC timing.

3. The apparatus of claim 1, wherein the amplifier is part of an integrator.

4. The apparatus of claim 1, wherein the circuitry is programmable.

5. The apparatus of claim 1, wherein the amplifier is a differential amplifier.

6. The apparatus of claim 1, wherein the ADC is a flash ADC.

7. The apparatus of claim 1 comprises a resistor coupled to the capacitor.

8. The apparatus of claim 1, wherein the DAC is a capacitive DAC.

9. The apparatus of claim 1, wherein the amplifier, capacitor, ADC, DAC, and circuitry are part of a sigma-delta modulator.

10. The apparatus of claim 9, wherein the sigma-delta modulator is a multi-order sigma delta modulator.

11. An apparatus comprising:

integrator having an input and an output;

an analog-to-digital converter (ADC) coupled to the output of the integrator;

a Digital-to-Analog converter (DAC) coupled to an output of the ADC and to the input of the integrator; and

circuitry coupled to the output of the ADC and the input of the integrator, wherein the DAC comprises;

a p-type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.

12. The apparatus of claim 11, wherein the circuitry is to compensate a delay of at least a portion of a loop formed by the integrator, the ADC, and the DAC.

13. The apparatus of claim 11, wherein the amplifier, capacitor, ADC, DAC, and circuitry are part of a sigma-delta modulator.

14. The apparatus of claim 13, wherein the sigma-delta modulator is a multi-order sigma delta modulator.

15. An apparatus comprising:

means for integrating an analog input current and generating an analog output;

means for converting the analog output to a corresponding digital output;

means for converting the corresponding digital output to an analog current, wherein the means for converting the corresponding digital output to the analog current includes a p-type current source a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor;

means for compensating an excess delay associated with the means for converting the analog output, and for generating an output current; and

means for summing the analog current with the analog input current and the output current.

16. The apparatus of claim 15, wherein the means for integrating includes means for amplifying the analog input current.

17. The apparatus of claim 15, wherein the means for integrating, the means converting the analog output, the means for converting the corresponding digital output, the means for compensating, and the means for summing are part of a sigma-delta modulator.

18. The apparatus of claim 17, wherein the sigma-delta modulator is a multi-order sigma delta modulator.

19. An apparatus comprising:

a first amplifier having an input and an output;

a second amplifier having an input and an output;

a resistor coupled to the output of the first amplifier and the input of the second amplifier;

a first capacitor coupled to the input and the output of the first amplifier;

a second capacitor coupled to the input and the output of the second amplifier;

a analog-to-digital converter coupled to the output of the second amplifier;

a digital-to-analog converter coupled to an output of the analog-to-digital converter, wherein an output of the digital-to-analog converter is coupled to the input of the first amplifier; and

a compensation circuit having an input coupled to the output of the analog-to-digital converter, wherein the compensation circuit has an output coupled to the input of the second amplifier, wherein the digital-to-analog converter comprises;

a p-type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.

20. The apparatus of claim 19, wherein the compensation circuit is to compensate an excess delay associated with the analog-to-digital converter and digital-to-analog converter timing.

21. A communication device comprising:

an antenna;

a low noise amplifier coupled to the antenna;

a mixer coupled to an output of the low noise amplifier;

a filter coupled to the output of the mixer; and

a sigma-delta modulator with an excess delay compensation circuitry, wherein the sigma-delta modulator is coupled to the first filter, wherein the sigma-delta modulator comprises a digital to analog converter which includes;

a p type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.

22. The communication device of claim 21, wherein the mixer is a first mixer, wherein the filter is a first filter, and wherein the sigma-delta modulator is a first sigma-delta modulator comprises:

a second mixer coupled to an output of the low noise amplifier;

a second filter coupled to the output of the second mixer; and

a second sigma-delta modulator with an excess delay compensation circuitry, wherein the second sigma-delta modulator is coupled to the second filter.

23. The communication device of claim 22, wherein the first mixer is to receive a first clock, wherein the second mixer is to receive a second clock, and wherein there the first clock and the second clock have different phases.

24. The communication device of claim 23, wherein each of the first and second sigma-delta modulators comprises:

an amplifier having an input and an output;

a capacitor coupled to the input and the output of the amplifier;

an analog-to-digital converter (ADC) coupled to the output of the amplifier;

a Digital-to-Analog converter (DAC) coupled to an output of the ADC and to the input of the amplifier; and

the excess delay compensation circuitry coupled to the output of the ADC and the output of the DAC, wherein the excess delay compensation circuitry is to compensate for an excess delay of at least a portion of a feedback path comprising the amplifier.

25. An apparatus comprising:

an integrator to integrate an analog input current and for generating an analog output;

a analog-to-digital converter to convert the analog output to a corresponding digital output;

a digital-to-analog converter to convert the corresponding digital output to an analog current;

circuit for compensating excess delay associated with the analog-to digital converter, wherein the circuit is to generate an output current; and

a node for summing the analog current with the analog input current and the output current, wherein the digital-to-analog converter comprises;

a p-type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.

26. The apparatus of claim 25, wherein the integrator, analog-to-digital converter, digital-to-analog converter, and circuit are part of a sigma-delta modulator.

27. The apparatus of claim 26, wherein the sigma-delta modulator is a multi-order sigma delta modulator.

28. An apparatus comprising:

an amplifier having an input and an output;

a capacitor coupled to the input and the output of the amplifier;

an analog-to-digital converter (ADC) coupled to the output of the amplifier;

a Digital-to-Analog converter (DAC) coupled to an output of the ADC and to the input of the amplifier; and

a circuitry coupled to the output of the ADC and the input of the amplifier, wherein the circuitry is to compensate for an excess delay of at least a portion of a feedback path comprising the ADC, wherein the DAC comprises;

a p-type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.

29. The apparatus of claim 28, wherein the amplifier, capacitor, ADC, DAC, and circuitry are part of a sigma-delta modulator.

30. The apparatus of claim 28, wherein the sigma-delta modulator is a multi-order sigma delta modulator.

31. The apparatus of claim 28, wherein the circuitry is to compensate the excess delay associated with the ADC and DAC timing.

32. The apparatus of claim 28, wherein the sigma-delta modulator is a multi-order sigma delta modulator.

33. A method comprising:

integrating an analog input current and generating an analog output;

converting the analog output to a corresponding digital output;

converting the corresponding digital output to an analog current;

compensating an excess delay associated with the means for converting the analog output, and generating an output current as a result of compensating; and

summing the analog current with the analog input current and the output current, wherein converting the corresponding digital output to the analog current is performed by a circuitry that comprises;

a p type current source;

a first p-type transistor coupled in series with the p-type current source;

a first n-type transistor coupled in series with the first p-type transistor; and

an n-type current source coupled in series with the first n-type transistor.