Array substrate, liquid crystal display panel and display device

• US 10,209,587 B2
• Filed: 09/13/2017
• Issued: 02/19/2019
• Est. Priority Date: 06/06/2017
• Status: Active Grant

• Current Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: Wu, Hao
• Primary Examiner(s): Kim, Richard H
• Application Number:
  US15/702,819
• Publication Number:
  US 20180348584A1
• Time in Patent Office: 524 Days
• Field of Search: None
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G02F 1/137 characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
• CPC Class Codes: G02F 1/13712 the liquid crystal having negative dielectric anisotropy
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/122 having a particular pattern
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes

Abstract

The present disclosure provides an array substrate, including: a base substrate, a plurality of scan lines; a plurality of data lines arranged by intersecting with the plurality of scan lines; a plurality of thin film transistors arranged in a matrix, each thin film transistor includes a gate electrode, an active layer and a drain electrode; a planarization layer covering the gate electrode, the active layer and the drain electrode, a position of the planarization layer corresponding to the drain electrode is provided with a through hole penetrating through the planarization layer, and the drain electrode is located in the through hole; a filling electrode, located in the through hole and connected with the drain electrode and covers the drain electrode; and a pixel electrode, indirectly connected with the drain electrode through the filling electrode.

Claims

1. An array substrate, comprising:

a base substrate;

a plurality of scan lines;

a plurality of data lines intersecting with the plurality of scan lines;

a plurality of thin film transistors arranged in a matrix, each thin film transistor comprising a gate electrode, an active layer and a drain electrode;

a planarization layer covering the gate electrode, the active layer and the drain electrode,

a filling electrode; and

a pixel electrode;

wherein a through hole is defined in a part of the planarization layer corresponding to the drain electrode, a width of the drain electrode is smaller than a width of a bottom of the through hole, and the drain electrode is located in an interior of the through hole;

wherein the filling electrode is located in the through hole, and the filling electrode is connected with the drain electrode and covers the drain electrode; and

wherein the pixel electrode extends through the through hole to connect with the filling electrode.

2. The array substrate according to claim 1, further comprising:

a common electrode, located between the planarization layer and the pixel electrode; and

a second insulating layer, located between the common electrode and the pixel electrode;

wherein the filling electrode and the common electrode are formed in a same layer.

3. The array substrate according to claim 2, further comprising:

a first insulating layer, provided between the planarization layer and the common electrode; and

an auxiliary filling piece, filled between each of two ends of the drain electrode and a side wall of the through hole;

wherein the auxiliary filling piece and the first insulating layer are formed in a same layer.

4. The array substrate according to claim 1, further comprising:

a touch electrode; and

a plurality of touch signal lines connected with a corresponding touch electrode;

wherein the filling electrode comprises a first electrode, and the first electrode and the touch signal lines are formed in a same layer.

5. The array substrate according to claim 4, wherein the touch electrode is located between the planarization layer and the pixel electrode, and a second insulating layer is provided between the common electrode and the pixel electrode.

6. The array substrate according to claim 5, wherein the filling electrode further comprises a second electrode, and the second electrode and the touch electrode are formed in a same layer.

7. The array substrate according to claim 4, wherein the touch signal lines is located between the planarization layer and the touch electrode, and a first insulating layer is provided between the touch signal lines and the touch electrode.

8. The array substrate according to claim 6, wherein during a display period, the touch electrode also serves as a common electrode.

9. A liquid crystal display panel, comprising an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate;

wherein the array substrate comprises;

a base substrate;

a plurality of scan lines;

a plurality of data lines intersecting with the plurality of scan lines;

a plurality of thin film transistors arranged in a matrix, each thin film transistor comprising a gate electrode, an active layer and a drain electrode;

a planarization layer covering the gate electrode, the active layer and the drain electrode,

a filling electrode; and

a pixel electrode;

wherein a through hole is defined in a part of the planarization layer corresponding to the drain electrode, a width of the drain electrode is smaller than a width of a bottom of the through hole, and the drain electrode is located in an interior of the through hole;

wherein the filling electrode is located in the through hole, and the filling electrode is connected with the drain electrode and covers the drain electrode; and

wherein the pixel electrode extends through the through hole to connect with the filling electrode.

10. The liquid crystal display panel according to claim 9, wherein the liquid crystal layer comprises a negative liquid crystal.

11. A display device, comprising a liquid crystal display panel, wherein the liquid crystal display panel comprises an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate;

wherein the array substrate comprises;

a base substrate;

a plurality of scan lines;

a plurality of data lines intersecting with the plurality of scan lines;

a plurality of thin film transistors arranged in a matrix, each thin film transistor comprising a gate electrode, an active layer and a drain electrode;

a planarization layer covering the gate electrode, the active layer and the drain electrode,

a filling electrode; and

a pixel electrode;

wherein a through hole is defined in a part of the planarization layer corresponding to the drain electrode, a width of the drain electrode is smaller than a width of a bottom of the through hole, and the drain electrode is located in an interior of the through hole;

wherein the filling electrode is located in the through hole, and the filling electrode is connected with the drain electrode and covers the drain electrode; and

wherein the pixel electrode extends through the through hole to connect with the filling electrode.