Exposure focus leveling method using region-differentiated focus scan patterns

• US 10,209,636 B1
• Filed: 03/07/2018
• Issued: 02/19/2019
• Est. Priority Date: 03/07/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Toda, Tohru, Izumi, Keisuke, Sano, Michiaki
• Primary Examiner(s): Riddle, Christina A
• Application Number:
  US15/914,504
• Time in Patent Office: 349 Days
• Field of Search: 355 52, 355 53, 355 55, 355 72, 355 77, 2504921, 2504922, 25049222, 2504931, 438 14
• CPC Class Codes: G03F 7/2004 characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light
• CPC Class Codes: G03F 7/2039 X-ray radiation
• CPC Class Codes: G03F 7/70483 Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70525 Controlling normal operating mode, e.g. matching different apparatus, remote control or prediction of failure
• CPC Class Codes: G03F 7/70641 Focus
• CPC Class Codes: G03F 7/70775 Position control, e.g. interferometers or encoders for determining the stage position
• CPC Class Codes: G03F 9/7003 Alignment type or strategy, e.g. leveling, global alignment
• CPC Class Codes: G03F 9/7026 Focusing
• CPC Class Codes: G03F 9/7034 Leveling
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/67259 Position monitoring, e.g. misposition detection or presence detection
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Pattern-dependent random deviations in measurement of optimal focus distances can be minimized by separating scan paths into multiple types of scan paths that scan only a respective predetermined image region in semiconductor dies. A substrate including in-process semiconductor dies is coated with a photoresist layer, and is located onto a stage in a lithographic exposure tool. Maps of optimal focus distances are generated by performing optimal focus distance scans that cover a respective subset of image regions having distinct image patterns. The substrate can be leveled with respect to an optics system of the lithographic exposure tool employing a weighted average of multiple maps of optimal focus distances. Once the substrate is leveled on the stage, a lithographic exposure process can be performed with enhanced uniformity in the focus distances across the in-process semiconductor dies.

Claims

1. A method of operating a lithographic exposure tool, comprising:

forming semiconductor dies arranged in a plurality of rows and columns in an array on a substrate, wherein the array has a first periodicity along a first horizontal direction and a second periodicity along a second horizontal direction within a horizontal plane that is parallel to a top surface of the substrate, and each semiconductor die includes a first image region and a second image region having a different pattern of structural components than the first image region;

applying a photoresist layer over the semiconductor dies;

loading the substrate on a stage in the lithographic exposure tool;

generating a first map of first optimal focus distances along first scan paths that extend along the first horizontal direction and over the first image regions of the semiconductor dies on the substrate, wherein the first scan paths do not cross any of the second image regions of the semiconductor dies;

generating a second map of second optimal focus distances along second scan paths that extend along the first horizontal direction and over the second image regions of the semiconductor dies on the substrate, wherein the second scan paths do not cross any of the first image regions of the semiconductor dies; and

leveling the substrate with respect to an optics system of the lithographic exposure tool.

2. The method of claim 1, wherein leveling the substrate with respect to the optics system of the lithographic exposure tool comprises employing a weighted average of the first map of first optimal focus distances and the second map of second optimal focus distances, and the method further comprises:

′

determining a first two-dimensional plane that provides a least root mean square distance deviation for the first map of first optimal focus distances; and

determining a second two-dimensional plane that provides a least root mean square distance deviation for the second map of second optimal focus distances, wherein the leveling of the substrate is performed employing the location of the first two-dimensional plane and the second two-dimensional plane with respect to the optics system.

3. The method of claim 2, further comprising determining a weighted two-dimensional plane within respective to the optics system by calculating a weighted average of the first two-dimensional plane and the second two-dimensional plane,

wherein leveling the substrate is performed to place a target focal plane within the photoresist layer on the substrate entirely within the weighted two-dimensional plane.

4. The method of claim 3, wherein the target focal plane within the photoresist layer is a two-dimensional plane that is parallel to a top surface of the photoresist layer and located between a bottom surface of the photoresist layer and the top surface of the photoresist layer, at the bottom surface of the photoresist layer, or at the top surface of the photoresist layer.

5. The method of claim 4, further comprising lithographically exposing the semiconductor dies after leveling the substrate with a via pattern,

wherein:

more via patterns are formed in the second image region of each semiconductor die than in the first image region of each semiconductor die;

a first weighting factor multiplied to the first two-dimensional plane for calculation of the weighted two-dimensional plane is less than a second weighting factor multiplied to the second two-dimensional plane for calculation of the weighted two-dimensional plane; and

the first weighting factor and the second weighting factor are positive and add up to 1.0.

6. The method of claim 3, wherein weighting factors multiplied to the first or second two-dimensional plane for calculation of the weighted two-dimensional plane are not proportional to a respective fraction of scanned areas in the first scan paths or the second scan paths with respect to total scanned areas of the semiconductor dies.

7. The method of claim 2, further comprising:

determining an x-direction tilt angle and a y-axis tilt angle for the first two-dimensional plane; and

determining an x-direction tilt angle and a y-axis tilt angle for the second two-dimensional plane, wherein the leveling of the substrate is performed employing the x-direction tilt angles and the y-direction tilt angles.

8. The method of claim 7, further comprising:

determining a weighted x-direction tilt angle within respective to the optics system by calculating a weighted average of the x-direction tilt angle of the first two-dimensional plane and the x-direction tilt angle of the second two-dimensional plane; and

determining a weighted y-direction tilt angle within respective to the optics system by calculating a weighted average of the y-direction tilt angle of the first two-dimensional plane and the y-direction tilt angle of the second two-dimensional plane,

wherein leveling the substrate is performed by tilting the substrate with the weighted x-direction tilt angle within a vertical plane including the x-direction and with the weighted y-direction tilt angle within a vertical plane including the y-direction.

9. The method of claim 8, wherein weighting factors multiplied to the x-direction tilt angle and the y-direction tilt angle of the first or second two-dimensional planes are not proportional to a respective fraction of scanned areas in the first scan paths or the second scan paths with respect to total scanned areas of the semiconductor dies.

10. The method of claim 9, further comprising lithographically exposing the semiconductor dies after leveling the substrate with a via pattern,

wherein:

more via patterns are formed in the second image region of each semiconductor die than in the first image region of each semiconductor die;

a first weighting factor multiplied to the x-direction tilt angle and the y-direction tilt angle of the first two-dimensional plane is less than a second weighting factor multiplied to the x-direction tilt angle and the y-direction tilt angle of the second two-dimensional plane; and

the first weighting factor and the second weighting factor are positive and add up to 1.0.

11. The method of claim 8, further comprising:

generating a third map of third optimal focus distances along the first scan paths after leveling of the substrate;

generating a fourth map of fourth optimal focus distances along the second scan paths after leveling the substrate; and

providing an additional leveling the substrate with respect to the optics system employing a weighted average of the third map of first optimal focus distances and the fourth map of second optimal focus distances.

12. The method of claim 1, wherein:

a total range of deviations of the first optimal focus distances for the semiconductor dies is reduced by leveling the substrate; and

a total range of deviations of the second optimal focus distances for the semiconductor dies is reduced by the leveling the substrate.

13. The method of claim 1, wherein:

the substrate comprises a semiconductor wafer;

the semiconductor dies are in-process semiconductor dies including at least one memory array region and at least one contact region of a three-dimensional memory device;

the first image regions comprise areas of instances of the at least one memory array region in the in-process semiconductor dies; and

the second image regions comprise areas of instances of the at least one contact region.

14. The method of claim 13, wherein the second image region comprises a pattern of stepped surfaces of word lines that continuously extend into an area of the first image region.

15. The method of claim 13, wherein:

the first image region comprises a memory plane comprising pattern of memory stack structures located within a memory array region of a respective semiconductor die and arranged as a two-dimensional array within the at least one memory array region; and

the first scan paths extend over the first image region and a third image region which comprises a pattern of sense amplifier peripheral devices located within a peripheral device region of the respective semiconductor die and laterally offset from the memory array region along the first horizontal direction.

16. The method of claim 1, wherein the second image regions have a narrower width along the second horizontal direction than the first image regions.

17. The method of claim 1, wherein each semiconductor die comprises an additional first image region having a same image as, or having a mirror image of, the first image region, and the first scan paths extend over the additional first image regions of the semiconductor dies on the substrate along the first horizontal direction.

18. The method of claim 1, wherein the lithographic exposure tool is a deep ultraviolet lithographic exposure tool, a mid-ultraviolet lithographic exposure tool, or an X-ray lithographic exposure tool.

19. A method of operating a lithographic exposure tool, comprising:

forming semiconductor dies arranged in a plurality of rows and columns in an array on a substrate, wherein the array has a first periodicity along a first horizontal direction and a second periodicity along a second horizontal direction within a horizontal plane that is parallel to a top surface of the substrate, and each semiconductor die includes a first image region comprising a NAND memory plane, at least one second image region comprising a NAND word line contact region which comprises a pattern of stepped surfaces of word lines that continuously extend into an area of the first image region along the second horizontal direction, and a third image region which comprises sense amplifier circuitry in a peripheral device region that is electrically connected to bit lines that laterally extend into the area of the first image region along the first horizontal direction

applying a photoresist layer over the semiconductor dies;

loading the substrate on a stage in the lithographic exposure tool;

generating a first map of first optimal focus distances along first scan paths that extend along the first horizontal direction and over the first and the third image regions of the semiconductor dies on the substrate, wherein the first scan paths do not cross any of the second image regions of the semiconductor dies;

generating a second map of second optimal focus distances along second scan paths that extend along the first horizontal direction and over the second image regions of the semiconductor dies on the substrate, wherein the second scan paths do not cross any of the first and third image regions of the semiconductor dies; and

leveling the substrate with respect to an optics system of the lithographic exposure tool.

20. The method of claim 19, wherein

each semiconductor die comprises at least two memory planes that are offset from each other in the second horizontal direction;

the at least one second image region in each of the semiconductor dies comprises an inner second image region located between the two memory planes, and at least one outer second image region located outside of the two memory planes; and

generating the second map comprises generating a first part of the second map along a first set of second scan paths that extend along the first horizontal direction and over the inner second image regions, and generating a second part of the second map along a second set of second scan paths that extend along the first horizontal direction and over the outer second image regions.