Semiconductor device, semiconductor system, and method of operating the semiconductor device

• US 10,209,734 B2
• Filed: 01/25/2017
• Issued: 02/19/2019
• Est. Priority Date: 01/25/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Min Joung, Kwon, Suk Nam, Lee, Jae Gon
• Primary Examiner(s): Choudhury, Zahid
• Application Number:
  US15/415,162
• Publication Number:
  US 20170212550A1
• Time in Patent Office: 755 Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 21/725 operating on a secure reference time value

Abstract

A clock management unit (CMU) includes a first clock control circuit controlling a first clock source, a second clock control circuit sending a first clock request to the first clock control circuit in response to an intellectual property (IP) block clock request from an IP block and controlling a second clock source, and a CMU controller. The second clock source receives a clock signal from the first clock source. A power management unit (PMU) sends a PMU clock request to the CMU controller. The CMU provides the clock signal to the IP block in response to the PMU clock request.

Claims

1. A semiconductor device, comprising:

a clock management unit (CMU) including a first clock control circuit controlling a first clock source, a second clock control circuit sending a first clock request to the first clock control circuit in response to an intellectual property (IP) block clock request from an IP block and controlling a second clock source, wherein the second clock source receives a clock signal from the first clock source, and a CMU controller; and

a power management unit (PMU) sending a PMU clock request to the CMU controller,

wherein the CMU provides the clock signal to the IP block in response to the PMU clock request.

2. The semiconductor device of claim 1,

wherein the PMU further sends a control command to the CMU, and

wherein the CMU controller controls the first or second clock control circuit according to the control command and then sends an acknowledgement to the PMU.

3. The semiconductor device of claim 2, further comprise:

a clock generator coupled to the first clock source; and

an oscillator coupled to the first clock source,

wherein the first clock source includes a multiplexer (MUX) circuit,

wherein the multiplexer (MUX) circuit of the first clock source is coupled to the clock generator and the oscillator, and

wherein the control command includes a PLL deactivation command for deactivating an operation of the clock generator and allowing the first clock source to receive a clock signal from the oscillator.

4. The semiconductor device of claim 3,

wherein the CMU controller sends a PLL clock request to the first clock control circuit according to the PLL deactivation command, and

wherein the first clock control circuit sends an acknowledgement to the CMU controller.

5. The semiconductor device of claim 2,

wherein the CMU further includes a third clock source,

wherein the third clock source is controlled by software, and

wherein the control command includes a forced hardware automatic clock gating command for controlling an operation of the third clock source with the CMU controller.

6. The semiconductor device of claim 2,

wherein the control command includes a clock-on command or a clock-off command for controlling an operation of at least one of the first clock source and the second clock source.

7. The semiconductor device of claim 6,

wherein the CMU controller sends a leaf clock request to the second clock control circuit according to the clock-on command or the clock-off command, and

wherein the second clock control circuit sends an acknowledgement to the CMU controller.

8. The semiconductor device of claim 6,

wherein the first clock control circuit sends a root clock state signal to the CMU controller.

9. The semiconductor device of claim 2,

wherein the CMU further includes a channel management circuit sending a second clock request to the second clock control circuit in response to the IP block clock request from the IP block, and

wherein the CMU controller controls the channel management circuit according to the control command and then sends an acknowledgement to the PMU.

10. The semiconductor device of claim 9,

wherein the control command includes a bus transaction termination command for terminating bus transactions between the channel management circuit and the IP block.

11. The semiconductor device of claim 10,

wherein the CMU controller sends a bus clock request to the channel management circuit according to the bus transaction termination command, and

wherein the channel management circuit sends an acknowledgement to the CMU controller.

12. A semiconductor device, comprising:

a CMU including a first clock control circuit controlling a first clock source, a second clock control circuit sending a first clock request to the first clock control circuit in response to an IP block clock request from an IP block, controlling a second clock source, the second clock source receiving a clock signal from the first clock source, and a CMU controller; and

a PMU sending a control command to the CMU controller and receiving an acknowledgement from the CMU controller after the CMU controller performs the control command received from the PMU,

wherein the CMU provides the clock signal to the IP block in response to control command.

13. The semiconductor device of claim 12,

wherein the CMU controller controls the first clock control circuit according to the control command and sends the acknowledgement to the PMU.

14. The semiconductor device of claim 13,

wherein the first clock source includes a multiplexer circuit coupled to a clock generator and an oscillator, and

wherein the control command includes a PLL deactivation command for deactivating an operation of the clock generator and allowing the first clock source to receive a clock signal from the oscillator.

15. The semiconductor device of claim 14,

wherein the CMU controller sends a PLL clock request to the first clock control circuit according to the PLL deactivation command, and

wherein the first clock control circuit sends an acknowledgement to the CMU controller.

16. The semiconductor device of claim 13,

wherein the CMU further includes a third clock source, which is controlled by software, and

wherein the control command includes a forced hardware automatic clock gating command so that the CMU controller controls an operation of the third clock source.

17. The semiconductor device of claim 13,

wherein the control command includes a clock-on command or a clock-off command for controlling an operation of the first or second clock source.

18. A semiconductor device, comprising:

a clock source generating a clock signal;

a plurality of clock components including a root clock component and a leaf clock component,

wherein the clock signal passes through the plurality of clock components, and

wherein the clock source is coupled to the root clock component,

a channel management circuit coupled to the leaf clock component;

an intellectual property (IP) block coupled to the channel management circuit and receiving the clock signal;

a CMU controller coupled to the root clock component and the channel management circuit; and

a PMU coupled to the CMU controller,

wherein the plurality of clock components is configured to send a clock request signal from the leaf clock component to the root clock component in response to an intellectual property (IP) block clock request and transfer the clock signal from the root clock component to the leaf clock component in response to an acknowledgement from a previous clock component.

19. The semiconductor device of claim 18,

wherein the channel management circuit ignores the IP block clock request in response to a command from the PMU.

20. The semiconductor device of claim 18,

wherein the clock source includes at least one of a PLL and an oscillator.