Power management architecture
First Claim
1. An integrated circuit comprising:
- a plurality of pipeline stage circuits;
a plurality of voltage regulators integrated into the integrated circuit with the plurality of pipeline circuits, each of the plurality of voltage regulators;
coupled to a respective pipeline stage circuit;
configured to supply a regulated supply voltage to the respective pipeline stage circuit; and
includes one or more energy storage components; and
a plurality of control circuits coupled to the plurality of pipeline stage circuits and the plurality of voltage regulators, wherein;
a given control circuit of the plurality of control circuits is coupled to an activity indicator for a given pipeline stage circuit of the plurality of pipeline circuits;
the given control circuit is configured to cause a given voltage regulator of the plurality of voltage regulators to supply power to the given pipeline stage circuit in response to the activity indicator indicating activity;
the given control circuit is configured to cause a clock to the given pipeline stage circuit to be gated in response to the activity indicator indicating no activity;
the given control circuit is configured to cause the clock to be ungated in response to the activity indicator indicating activity and further in response to an expiration of a delay from the power being supplied to the given power supply circuit; and
the gated clock is not toggling and the ungated clock is toggling.
1 Assignment
0 Petitions
Accused Products
Abstract
In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.
11 Citations
18 Claims
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1. An integrated circuit comprising:
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a plurality of pipeline stage circuits; a plurality of voltage regulators integrated into the integrated circuit with the plurality of pipeline circuits, each of the plurality of voltage regulators; coupled to a respective pipeline stage circuit; configured to supply a regulated supply voltage to the respective pipeline stage circuit; and includes one or more energy storage components; and a plurality of control circuits coupled to the plurality of pipeline stage circuits and the plurality of voltage regulators, wherein; a given control circuit of the plurality of control circuits is coupled to an activity indicator for a given pipeline stage circuit of the plurality of pipeline circuits; the given control circuit is configured to cause a given voltage regulator of the plurality of voltage regulators to supply power to the given pipeline stage circuit in response to the activity indicator indicating activity; the given control circuit is configured to cause a clock to the given pipeline stage circuit to be gated in response to the activity indicator indicating no activity; the given control circuit is configured to cause the clock to be ungated in response to the activity indicator indicating activity and further in response to an expiration of a delay from the power being supplied to the given power supply circuit; and the gated clock is not toggling and the ungated clock is toggling. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An apparatus comprising:
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a plurality of pipeline stage circuits; and a plurality of control circuits coupled to the plurality of pipeline stage circuits, wherein; a given control circuit of the plurality of control circuits is coupled to an activity indicator for a given pipeline stage circuit of the plurality of pipeline circuits; the activity indicator indicates whether or not there is activity at an input to the given pipeline stage circuit; the given control circuit of the plurality of control circuits is coupled to a second indicator that indicates, in advance of the activity indicator, that the activity indicator will be indicating activity at a subsequent point in time; and the given control circuit is configured to cause power and clock to be supplied to the given pipeline stage circuit in response to the second indicator, wherein supplying the clock includes ungating the clock so that the clock begins to toggle to the given pipeline stage circuit after a delay expires from causing the power to be supplied to the given pipeline circuit, wherein the clock is gated prior to being ungated by the given control circuit, and wherein the gated clock is not toggling and the ungated clock is toggling; and a controller circuit coupled to the plurality of control circuits and the plurality of pipeline stage circuits, wherein the controller circuit is configured to generate at least the second indicator for the given pipeline stage circuit. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification