Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the data

• US 10,209,902 B1
• Filed: 02/14/2018
• Issued: 02/19/2019
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sheredy, Joseph, Nguyen, Lau
• Primary Examiner(s): Nguyen, Hiep T
• Application Number:
  US15/897,000
• Time in Patent Office: 370 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Claims

1. A method for storing data in a memory module comprising (i) a single-level cell memory block and (ii) a multi-level cell memory block, the method comprising:

storing the data in the multi-level cell memory block;

subsequent to storing the data in the multi-level cell memory block, updating the data for one or more times;

tracking, by a cache system, a frequency with which the data stored in the multi-level cell memory block is updated;

based at least in part on the frequency with which the data stored in the multi-level cell memory block is updated, determining, by a memory controller, that the data is to be stored in the single-level cell memory block; and

based on determining that the data is to be stored in the single-level cell memory block, storing, by the memory controller, the data in the single-level cell memory block.

2. The method of claim 1, wherein storing the data in the single-level cell memory block further comprises:

subsequent to determining that the data is to be stored in the single-level cell memory block, determining that the data is to be updated to a modified data; and

in response to (i) determining that the data is to be stored in the single-level cell memory block and (ii) determining that the data is to be updated, writing the modified data in the single-level cell memory block.

3. The method of claim 2, further comprising:

while writing the modified data in the single-level cell memory block, refraining from updating the data stored in the multi-level cell memory.

4. The method of claim 1, wherein determining that the data is to be stored in the single-level cell memory block further comprises:

in response to the frequency with which the data stored in the multi-level cell memory block is updated being higher than a threshold frequency, determining that the data is to be stored in the single-level cell memory block.

5. The method of claim 1, wherein determining that the data is to be stored in the single-level cell memory block further comprises:

in response to tracking the frequency with which the data stored in the multi-level cell memory block is updated, categorizing the data as frequently updated data; and

in response to categorizing the data as the frequently updated data, determining that the data is to be stored in the single-level cell memory block.

6. The method of claim 1, further comprising:

subsequent to storing the data in the single-level cell memory block, overwriting the data stored in the multi-level cell memory block with new data.

7. The method of claim 1, further comprising:

subsequent to storing the data in the single-level cell memory block, erasing the data stored in the multi-level cell memory block.

8. The method of claim 1, wherein:

the single-level cell memory block comprises a plurality of single-level memory cells; and

the multi-level cell memory block comprises a plurality of multi-level memory cells.

9. A system for storing data in a memory module, the system comprising:

the memory module comprising (i) a single-level cell memory block and (ii) a multi-level cell memory block;

a cache system configured to track a frequency with which the data stored in the single-level cell memory block is updated; and

a memory controller configured to

store the data in the single-level cell memory block,

based at least in part on the frequency with which the data stored in the single-level cell memory block is updated, determine that the data is to be stored in the multi-level cell memory block, and

based on determining that the data is to be stored in the multi-level cell memory block, store the data in the multi-level cell memory block.

10. The system of claim 9, wherein the memory controller is configured to store the data in the multi-level cell memory block by:

subsequent to determining that the data is to be stored in the multi-level cell memory block, determining that the data is to be updated to a modified data; and

in response to (i) determining that the data is to be stored in the multi-level cell memory block and (ii) determining that the data is to be updated, writing the modified data in the multi-level cell memory block.

11. The system of claim 9, wherein the memory controller is configured to determine that the data is to be stored in the multi-level cell memory block by:

in response to the frequency with which the data stored in the single-level cell memory block is updated being lower than a threshold frequency, determining that the data is to be stored in the multi-level cell memory block.

12. The system of claim 9, wherein the memory controller is configured to determine that the data is to be stored in the multi-level cell memory block by:

in response to tracking the frequency with which the data stored in the single-level cell memory block is updated, categorizing the data as infrequently updated data; and

in response to categorizing the data as the infrequently updated data, determining that the data is to be stored in the multi-level cell memory block.

13. The system of claim 9, wherein the memory controller is further configured to:

subsequent to storing the data in the multi-level cell memory block, overwrite the data stored in the single-level cell memory block with new data.

14. The system of claim 9, wherein the memory controller is further configured to:

subsequent to storing the data in the multi-level cell memory block, erase the data stored in the single-level cell memory block.

15. The system of claim 9, wherein the single-level cell memory block comprises a plurality of single-level memory cells.

16. The system of claim 9, wherein the multi-level cell memory block comprises a plurality of multi-level memory cells.

17. A method for storing data in a memory module comprising (i) a single-level cell memory block and (ii) a multi-level cell memory block, the method comprising:

storing the data in the multi-level cell memory block;

subsequent to storing the data in the multi-level cell memory block, updating the data for one or more times;

tracking, by a cache system, a frequency with which the data stored in the multi-level cell memory block is updated;

based at least in part on the frequency with which the data stored in the multi-level cell memory block is updated, determining, by a memory controller, that the data is to be stored in the single-level cell memory block;

subsequent to determining that the data is to be stored in the single-level cell memory block, receiving, by the memory controller, a command to update the data such that the data, subsequent to the update, is to be updated data; and

in response to (i) determining that the data is to be stored in the single-level cell memory block and (ii) receiving the command to update the data, writing, by the memory controller, the updated data to the single-level cell memory block, instead of updating the data in the multi-level cell memory block.

18. The method of claim 17, wherein determining that the data is to be stored in the single-level cell memory block further comprises:

in response to the frequency with which the data stored in the multi-level cell memory block is updated being higher than a threshold frequency, determining that the data is to be stored in the single-level cell memory block.

19. The method of claim 17, further comprising:

subsequent to storing the data in the single-level cell memory block, erasing the data stored in the multi-level cell memory block or overwriting the data stored in the multi-level cell memory block with new data.

20. The method of claim 17, wherein:

the single-level cell memory block comprises a plurality of single-level memory cells; and

the multi-level cell memory block comprises a plurality of multi-level memory cells.