Queue control for shared memory access

• US 10,209,925 B2
• Filed: 12/11/2017
• Issued: 02/19/2019
• Est. Priority Date: 04/28/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Katayama, Yasunao
• Primary Examiner(s): Patel, Kaushikkumar M
• Application Number:
  US15/837,992
• Publication Number:
  US 20180314463A1
• Time in Patent Office: 435 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags

Abstract

A memory controller is provided for accessing shared memory objects by read and write requests made to a memory. The memory controller includes a list for registering address locations of the shared objects in the memory, and having slots for a lock bit. The memory controller includes a read wait queue and a write wait queue for selectively inputting, outputting, holding, and purging requests. The memory controller includes a read initiated queue and a write initiated queue for selectively inputting and purging requests transferred from the read wait queue and the write wait queue, respectively, upon memory access initiation and completion. The memory controller includes a controller for controlling the wait queues using policies by determining which requests to output, hold, and purge, based on a list entry, a lock bit and TTL information set to each request upon a hold being applied thereto and decremented in each cycle.

Claims

1. A memory controller for accessing shared memory objects from local and remote locations by read requests and write requests made to a memory, the memory controller comprising:

a lock address list configured to register address locations of the shared memory objects in the memory, and having a plurality of slots each associated with a lock bit;

a read wait queue and a write wait queue configured to selectively input, output, hold, and purge the requests from processor cores and network inputs and outputs;

a read initiated queue and a write initiated queue configured to selectively input and purge the requests transferred from the read wait queue and the write wait queue, respectively, upon initiation and completion of corresponding accesses to the memory; and

a queue controller configured to control the wait queues using policies by determining which of the requests to output, which of the requests to hold, and which of the requests to purge, based on an entry of the lock address list, a status of a corresponding lock bit and Time To Live information set to each of the requests upon a hold being applied thereto and decremented in each cycle.

6. The memory controller of claim 1, wherein the queue controller is configured to purge a selected on-hold entry in one of the wait queues, responsive to the one of the wait queues being substantially close to full.

7. The memory controller of claim 1, wherein the queue controller is configured to notify one or more upper streams to cease sending further requests, responsive to one of the wait queues being substantially close to full.

2. The memory controller of 1, further comprising a read reserved queue configured to selectively input, hold and purge the requests transferred from the read initiated queue upon initiation of the shared memory object read accesses and held or purged based on the following write requests and Time To Live information set to each request upon hold and decremented in each cycle.

3. The memory controller of claim 2, wherein the queue controller is configured to purge a selected on-hold entry in the read reserve queue, responsive to the read reserve queue being substantially close to full.

4. The memory controller of claim 2, wherein the read reserved queue is configured to manage multiple pending Load-Link and Store Conditional (LL/SC) operations by accepting multiple Load-Links until one of the multiple Load-Links successfully completes a store operation.

5. The memory controller of claim 2, wherein the read reserved queue is configured for use only with first half accesses from among the first half accesses and corresponding second half accesses in the lock address list.

8. A computer processing system, comprising:

a processor;

a non-volatile memory; and

a memory controller for accessing shared memory objects from local and remote locations by read requests and write requests made to the non-volatile memory, the memory controller including;

a lock address list configured to register address locations of the shared memory objects in the non-volatile memory, and having a plurality of slots each associated with a lock bit;

a read wait queue and a write wait queue configured to selectively input, output, hold, and purge the requests from processor cores and network inputs and outputs;

a read initiated queue and a write initiated queue configured to selectively input and purge the requests transferred from the read wait queue and the write wait queue, respectively, upon initiation and completion of corresponding accesses to the non-volatile memory; and

a queue controller configured to control the wait queues using policies by determining which of the requests to output, which of the requests to hold, and which of the requests to purge, based on an entry of the lock address list, a status of a corresponding lock bit and Time To Live information set to each of the requests upon a hold being applied thereto and decremented in each cycle.

9. The computer processing system of claim 8, further comprising a read reserved queue configured to selectively input, hold and purge the requests transferred from the read initiated queue upon completion of the shared memory object read accesses and held or purged based on the following write requests and Time To Live information set to each request upon hold and decremented in each cycle.

10. The computer processing system of claim 9, wherein the processor is configured to notify a request source of a memory error exemption, responsive to a condition applicable to the wait queues and the initiated queues and inapplicable to the read reserved queue, the condition being a lock address hit entry purged unsuccessfully in any of the wait queues and the initiated queues.

11. The computer processing system of claim 8, wherein the processor is configured to notify a request source of a memory error exemption, responsive to a lock address hit entry being purged unsuccessfully in any of the wait queues and the initiated queues.

12. The computer processing system of claim 8, wherein the processor is configured to disable context switching operations during a paired memory access to the non-volatile memory.

13. The computer processing system of claim 8, wherein at least a portion of the memory controller is comprised in the non-volatile memory.