Tracking of optimum read voltage thresholds in nand flash devices

• US 10,210,926 B1
• Filed: 09/15/2017
• Issued: 02/19/2019
• Est. Priority Date: 09/15/2017
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Amiri, Behzad, Miladinovic, Nenad
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US15/705,678
• Time in Patent Office: 522 Days
• Field of Search: 36518503, 36518509, 36518511, 36518512, 36518518, 36518524, 36518529, 36518533, 3651852
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A method for biasing read voltage for flash memory in a storage system, performed by the storage system, is provided. The method includes tracking bit flips in a first direction and bit flips in a second direction in data reads of the flash memory in the storage system, based on error correction of the data reads. The method includes comparing or forming a ratio of the bit flips in the first direction to the bit flips in the second direction or the bit flips in one of the first direction or the second direction to a total number of bit flips. The method includes adjusting read voltage level for the flash memory in the storage system, based on the comparing or the forming the ratio.

Claims

1. A method for biasing read voltage for flash memory in a storage system, performed by the storage system, comprising:

tracking bit flips in a first direction and bit flips in a second direction in data reads of the flash memory in the storage system, based on error correction of the data reads, wherein each bit flip comprises a data read of a bit read in error in a specified direction;

comparing or forming a ratio of the bit flips in the first direction to the bit flips in the second direction or the bit flips in one of the first direction or the second direction to a total number of bit flips; and

adjusting read voltage level for the flash memory in the storage system, based on the comparing or the forming the ratio.

2. The method of claim 1, wherein:

the tracking comprises tracking individual blocks of the flash memory; and

the adjusting the read voltage level comprises adjusting the read voltage level for a logical unit number (LUN) of the flash memory.

3. The method of claim 1, wherein the adjusting the read voltage comprises adjusting the read voltage for each of a plurality of read voltage levels of multilevel cell (MLC) flash memory.

4. The method of claim 1, wherein the adjusting the read voltage level is responsive to exceeding a threshold in the comparing or the forming the ratio.

5. The method of claim 1, wherein the adjusting the read voltage level comprises adjusting the read voltage level from a previous adjusted read voltage level, without returning to a default read voltage level between adjustments to the read voltage level.

6. The method of claim 1, wherein the adjusting the read voltage level comprises communicating a command that indicates a read voltage level and an offset value for the read voltage level, to the flash memory.

7. The method of claim 1, wherein:

the tracking is of bit flips relative to a specified page type in multilevel cell flash memory; and

the adjusting the read voltage level comprises determining an offset for a read voltage level that affects the bit flips relative to the specified page type, and extrapolating at least one further offset for read voltage levels of the multilevel cell flash memory based on the offset.

8. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to perform a method comprising:

determining a quantity of bit flips from a logical 0 to a logical 1 or a quantity of bit flips from a logical 1 to a logical 0 in data reads of the flash memory in the storage system, based on error correction of the data reads, wherein each bit flip comprises a data read of a bit read in error in a specified direction;

forming a comparison or a ratio of the quantity of the bit flips from the logical 0 to the logical 1 or the quantity of the bit flips from the logical 1 to the logical 0 to each other or to a total number of bit flips; and

setting read voltage level for the flash memory in the storage system, based on the comparison or the ratio.

9. The computer-readable media of claim 8, wherein:

the determining is on a per block basis; and

the setting is on a per logical unit number (LUN) of the flash memory basis.

10. The computer-readable media of claim 8, wherein the setting the read voltage comprises setting the read voltage for each of a plurality of read voltage levels of multilevel cell (MLC) flash memory comprising two or more bits per cell.

11. The computer-readable media of claim 8, wherein the setting the read voltage level is responsive to the comparison or the ratio exceeding a threshold.

12. The computer-readable media of claim 8, wherein the setting the read voltage level comprises revising the read voltage level from a previous revised read voltage level, and not returning to a default read voltage level between revisions to the read voltage level.

13. The computer-readable media of claim 8, wherein the setting the read voltage level comprises sending to the flash memory a command with an address that indicates a read voltage level and data that indicates an offset value for the read voltage level.

14. The computer-readable media of claim 8, wherein the method further comprises:

tracking bit flips relative to a specified page type in multilevel cell flash memory, the specified page type being upper page, lower page or extra page;

determining a value for a read voltage level that affects the bit flips relative to the specified page type; and

extrapolating at least one further value for read voltage levels of the multilevel cell flash memory based on the determined value, wherein the setting is based on the determining the value and the extrapolating the at least one further value.

15. A storage system, comprising:

flash memory having adjustable read voltage level; and

one or more processors, configurable to;

perform error correction of data reads of the flash memory;

track bit flips in the data reads, based on the error correction, wherein each bit flip comprises a data read of a bit read in error in a specified direction;

form a comparison or a ratio of a quantity of bit flips in a first direction or a quantity of bit flips in a second direction to each other or to a total number of bit flips; and

direct a read voltage level for the flash memory, based on the comparison or the ratio.

16. The storage system of claim 15, further comprising:

a first memory, configurable by the one or more processors to have a data structure that records a block identifier for each of a plurality of blocks of the flash memory, a bit flip comparison or bit flip ratio for each of the plurality of blocks, and a plurality of offsets for read voltage levels for each of the plurality of blocks.

17. The storage system of claim 15, wherein:

to track the bit flips is to track the bit flips of each of a plurality of blocks of the flash memory;

to form the comparison or the ratio is to form the comparison or the ratio for one of the plurality of blocks of the flash memory; and

to direct the read voltage level is to direct the read voltage level of a logical unit number (LUN) of the flash memory that includes the one of the plurality of blocks of the flash memory.

18. The storage system of claim 15, wherein the one or more processors and the flash memory are configurable so that the read voltage level for the flash memory remains as directed, until a next read voltage level is directed, without returning to a default read voltage level.

19. The storage system of claim 15, wherein:

to direct the read voltage level for the flash memory is triggered by the comparison or the ratio exceeding a threshold; and

to direct the read voltage level for the flash memory comprises sending a command, with read voltage level selection and read voltage level value, to the flash memory.

20. The storage system of claim 15, wherein:

to track the bit flips and to form the comparison or the ratio is relative to a specified page type in multilevel cell flash memory;

the read voltage level is related to the bit flips and the specified page type; and

the one or more processors are further configurable to direct further read voltage levels for the flash memory based on extrapolation from the read voltage level.