Semiconductor package and method of fabricating the same

• US 10,211,163 B2
• Filed: 02/13/2018
• Issued: 02/19/2019
• Est. Priority Date: 09/17/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., Samsung Electronics Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yeongseok
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US15/895,411
• Publication Number:
  US 20180174979A1
• Time in Patent Office: 371 Days
• Field of Search: 257789
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package including a marking film and a method of fabricating the same are provided wherein a marking film including a thermoreactive layer may be applied to a molding layer to protect a semiconductor chip under the molding layer and to efficiently perform a marking process. The thickness of the molding layer may thereby be reduced so the entire thickness of the semiconductor package may be reduced. Also, it is possible to prevent warpage of the semiconductor package through the marking film, provide the surface of the semiconductor package with gloss and freely adjust the color of the surface of the semiconductor package.

Claims

1. A semiconductor package comprising:

a semiconductor chip; and

a marking film on the semiconductor chip,

the marking film including a reflection layer for reflecting an electromagnetic wave,

the marking film including a thermoreactive layer on the reflection layer, and

the thermoreactive layer being configured to form a discoloration region in response to the electromagnetic wave.

2. The semiconductor package of claim 1, further comprising:

a molding layer between the semiconductor chip and the reflection layer.

3. The semiconductor package of claim 2, wherein

a distance between a top surface of the molding layer and a top surface of the semiconductor chip is in a range of about 1 μ

m to 40 μ

m.

4. The semiconductor package of claim 1,

wherein a thickness of the marking film is in a range between 5 μ

m and 40 μ

m.

5. The semiconductor package of claim 1, further comprising:

a base film on the marking film, wherein

the marking film is configured to separate from the base film to expose an upper surface of the marking film.

6. The semiconductor package of claim 5, wherein

the base film includes a release layer,

the release layer includes a release agent, and

the marking film is configured to separate from the release layer to expose the upper surface of the marking film.

7. The semiconductor package of claim 6, wherein

the release agent of the release layer is a silicone release agent, an epoxy release agent, or a fluorine release agent.

8. The semiconductor package of claim 6, wherein

the base film further includes a base layer on the release layer.

9. The semiconductor package of claim 5, wherein

the base film includes a base layer, and

the base layer has a releasing property.

10. The semiconductor package of claim 1, wherein

the reflection layer includes a reflection material for reflecting the electromagnetic wave, and

the reflection material includes at least one of Sb₂O₃, BaSO₄, (PbCO₃)₂Pb(OH)₂, TiO₂, ZnO, ZnS, Al₂O₃, or a combination thereof.

11. The semiconductor package of claim 1, wherein

the thermoreactive layer includes a light absorber and at least one of a discoloration material or a carbonization material.

12. The semiconductor package of claim 11, wherein

the light absorber includes one of carbon black, titanium black, Fe₃O₄, and mordant black.

13. The semiconductor package of claim 11, wherein

the thermoreactive layer includes the discoloration material, and

the discoloration material includes one of thermochromic material, photochromic material, ionochromic material, electrochromic material, solvatochromic material, piezochromic material, gasochromic material, vapochromic material or chronochromic material.

14. The semiconductor package of claim 11, wherein

the thermoreactive layer includes the carbonization material, and

the carbonization material includes one of acrylic, phenolic, epoxy, urethane, polyamide or polyolefin.

15. The semiconductor package of claim 1, wherein

the reflection layer and the thermoreactive layer include a thermosetting resin.

16. The semiconductor package of claim 1, wherein

the thermoreactive layer includes a dye.

17. The semiconductor package of claim 1, wherein

the semiconductor chip includes a memory element.

18. The semiconductor package of claim 1, wherein

the semiconductor chip includes a non-memory element.

19. The semiconductor package of claim 1, further comprising:

connection terminals connected to a bottom surface of the semiconductor chip, wherein

the marking film is on a top surface of the semiconductor chip.