Display device including transistor and manufacturing method thereof

• US 10,211,231 B2
• Filed: 11/30/2017
• Issued: 02/19/2019
• Est. Priority Date: 07/03/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Sasaki, Toshinari, Hosoba, Miyuki
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US15/827,318
• Publication Number:
  US 20180083049A1
• Time in Patent Office: 446 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a first gate electrode over a substrate;

a first gate insulating layer over the first gate electrode;

an oxide semiconductor layer over the first gate insulating layer;

a first insulating layer over the oxide semiconductor layer;

a source electrode and a drain electrode over the first insulating layer;

a second insulating layer over the source electrode and the drain electrode; and

a second gate electrode over the second insulating layer;

a resin layer over the second gate electrode;

a pixel electrode over the resin layer;

a light emitting layer over the pixel electrode; and

an electrode over the light emitting layer,

wherein the first insulating layer and the second insulating layer are configured to be a second gate insulating layer,

wherein the second gate electrode comprises a transparent conductive layer,

wherein the second gate electrode overlaps the source electrode and the drain electrode,

wherein in a channel length direction of the transistor, a length of the first gate electrode is larger than a length of the oxide semiconductor layer, and

wherein in the channel length direction of the transistor, a length of the second gate electrode is smaller than the length of the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the first insulating layer is configured to be a channel protective film.

3. The semiconductor device according to claim 1, wherein the resin layer is a planarization layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a microcrystalline region.

6. A semiconductor device comprising:

a first conductive layer over a substrate;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer over the first insulating layer;

a second conductive layer in contact with a top surface of the oxide semiconductor layer;

a third conductive layer in contact with the top surface of the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer;

a fourth conductive layer over the second insulating layer; and

a metal layer for shielding at least part of the oxide semiconductor layer from light,

wherein the first conductive layer comprises a region configured to serve as a first gate of a transistor,

wherein the fourth conductive layer comprises a region configured to serve as a second gate of the transistor,

wherein in a channel length direction of the transistor, a length of the first conductive layer is larger than a length of the oxide semiconductor layer,

wherein in the channel length direction of the transistor, a length of the fourth conductive layer is smaller than the length of the oxide semiconductor layer,

wherein the fourth conductive layer transmits light,

wherein the oxide semiconductor layer comprises a first region and a second region,

wherein the first region overlaps with the second conductive layer or the third conductive layer,

wherein the second region does not overlap with the second conductive layer and the third conductive layer,

wherein a thickness of the oxide semiconductor layer in the second region is smaller than a thickness of the oxide semiconductor layer in the first region, and

wherein the metal layer overlaps with the second region.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

8. The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises a microcrystalline region.

9. A semiconductor device comprising:

a first conductive layer over a substrate;

a first insulating layer over the first conductive layer;

an oxide semiconductor layer over the first insulating layer;

a second conductive layer in contact with a top surface of the oxide semiconductor layer;

a third conductive layer in contact with the top surface of the oxide semiconductor layer;

a second insulating layer over the oxide semiconductor layer;

a fourth conductive layer over the second insulating layer; and

a metal layer for shielding at least part of the oxide semiconductor layer from light,

wherein the first conductive layer comprises a region configured to serve as a first gate of a transistor,

wherein the fourth conductive layer comprises a region configured to serve as a second gate of the transistor,

wherein in a channel length direction of the transistor, a length of the first conductive layer is larger than a length of the oxide semiconductor layer,

wherein in the channel length direction of the transistor, a length of the fourth conductive layer is smaller than the length of the oxide semiconductor layer,

wherein the fourth conductive layer transmits light, and

wherein the metal layer overlaps with the fourth conductive layer and the oxide semiconductor layer.

10. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

11. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises a microcrystalline region.