Method for manufacturing semiconductor device

• US 10,211,240 B2
• Filed: 12/11/2017
• Issued: 02/19/2019
• Est. Priority Date: 10/22/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Sasagawa, Shinya, Muraoka, Taiga
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Mustapha, Abdulfattah
• Application Number:
  US15/837,552
• Publication Number:
  US 20180108680A1
• Time in Patent Office: 435 Days
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a transistor comprising;

a first metal layer;

a first insulating layer over the first metal layer;

an oxide semiconductor film over the first insulating layer;

a second metal layer and a third metal layer over the first insulating layer, the second metal layer and the third metal layer comprising copper; and

a second insulating layer over the oxide semiconductor film, the second metal layer and the third metal layer,

wherein the first metal layer is formed by a stack of a first titanium film and a first copper film,

wherein the second metal layer and the third metal layer are electrically connected to the oxide semiconductor film,

wherein the oxide semiconductor film comprises a channel region of the transistor, and

wherein the first metal layer comprises a gate electrode of the transistor.

2. The semiconductor device according to claim 1,

wherein each of the second metal layer and the third metal layer is formed by a stack of a second titanium film and a second copper film.

3. The semiconductor device according to claim 1,

wherein the second metal layer covers the oxide semiconductor film and is in direct contact with one of sides edge of the oxide semiconductor film.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises a first oxide semiconductor layer and a second oxide semiconductor layer, and

wherein the second oxide semiconductor layer is over the first oxide semiconductor layer and is stacked on the first oxide semiconductor layer.

5. The semiconductor device according to claim 4,

wherein the second oxide semiconductor layer is not stacked on the first oxide semiconductor layer on the channel region.

6. The semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises a region overlapping the second metal layer, and

wherein a thickness of the channel region is thinner than the region.

7. The semiconductor device according to claim 1,

wherein the second insulating layer is directly in contact with the channel region.

8. The semiconductor device according to claim 1,

wherein in a channel length direction of a bottom surface of the second metal layer is longer than a top surface of the second metal layer, and

wherein the channel length direction of a bottom surface of the third metal layer is longer than a top surface of the third metal layer.

9. The semiconductor device according to claim 2,

wherein in a first region the second titanium film is in contact with the second insulating layer, and

the first region overlaps with the gate electrode.

10. A semiconductor device comprising:

a transistor comprising;

a first metal layer;

a first insulating layer over the first metal layer;

an oxide semiconductor film over the first insulating layer;

a second metal layer and a third metal layer over the first insulating layer, the second metal layer and the third metal layer comprising copper; and

a second insulating layer over the oxide semiconductor film, the second metal layer and the third metal layer,

wherein the first metal layer is formed by a stack of a first titanium film and a first copper film,

wherein the oxide semiconductor film comprises indium, gallium, and zinc,

wherein the second metal layer and the third metal layer are electrically connected to the oxide semiconductor film,

wherein the oxide semiconductor film comprises a channel region of the transistor, and

wherein the first metal layer comprises a gate electrode of the transistor.

11. The semiconductor device according to claim 10,

wherein each of the second metal layer and the third metal layer is formed by a stack of a second titanium film and a second copper film.

12. The semiconductor device according to claim 10,

wherein the second metal layer covers the oxide semiconductor film and is in direct contact with one of sides edge of the oxide semiconductor film.

13. The semiconductor device according to claim 10,

wherein the oxide semiconductor film comprises a first oxide semiconductor layer and a second oxide semiconductor layer, and

wherein the second oxide semiconductor layer is over the first oxide semiconductor layer and is stacked on the first oxide semiconductor layer.

14. The semiconductor device according to claim 13,

wherein the second oxide semiconductor layer is not stacked on the first oxide semiconductor layer on the channel region.

15. The semiconductor device according to claim 10,

wherein the oxide semiconductor film comprises a region overlapping the second metal layer, and

wherein a thickness of the channel region is thinner than the region.

16. The semiconductor device according to claim 10,

wherein the second insulating layer is directly in contact with the channel region.

17. The semiconductor device according to claim 10,

wherein in a channel length direction of a bottom surface of the second metal layer is longer than a top surface of the second metal layer, and

wherein the channel length direction of a bottom surface of the third metal layer is longer than a top surface of the third metal layer.

18. The semiconductor device according to claim 11,

wherein in a first region the second titanium film is in contact with the second insulating layer, and

the first region overlaps with the gate electrode.