Manufacturing methods of JFET-type compact three-dimensional memory

• US 10,211,258 B2
• Filed: 03/09/2017
• Issued: 02/19/2019
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Zarroli, Michael C
• Application Number:
  US15/455,122
• Publication Number:
  US 20170186817A1
• Time in Patent Office: 712 Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/66893 with a PN junction gate, i.e. JFET
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/043 by implantation
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes

Abstract

Manufacturing methods of JFET-type compact three-dimensional memory (3D-M_C) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

Claims

1. A manufacturing method of a JFET-type compact three-dimensional memory (3D-Mc) including a decoding device and a memory device on a memory level above a semiconductor substrate, comprising the steps of:

1) forming a bottom electrode comprising a heavily-doped semiconductor material and a memory layer on said memory level;

2) applying a photo-resist layer and forming a hole therein at the location of said decoding device;

3) etching said memory layer under said hole;

performing an ion-implant step to counter-dope said heavily-doped semiconductor material under said hole to a lightly-doped semiconductor material, then removing said photo-resist layer;

4) etching said memory layer and said bottom electrode to define at least a x-line;

5) depositing and etching a high-conductive material to define at least a y-line and a control-line (c-line);

wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

2. The method according to claim 1, wherein the overlap portion and the non-overlap portions of said x-line with said y-line are both highly-conductive.

3. The method according to claim 1, wherein said memory device is a two-terminal device.

4. The method according to claim 1, wherein

the overlap portion of said x-line with said c-line is semi-conductive;

and,

the non-overlap portions of said x-line with said c-line are highly-conductive.

5. The method according to claim 1, wherein said decoding device is a three-terminal device.

6. The method according to claim 1, wherein said decoding device comprises a pass-transistor.

12. The method according to claim 1, wherein said decoding device is a three-terminal device.

13. The method according to claim 1, wherein said decoding device comprises a pass-transistor.

7. A manufacturing method of a JFET-type compact three-dimensional memory (3D-Mc) including a decoding device and a memory device on a memory level above a semiconductor substrate, comprising the steps of:

1) forming a bottom electrode and a memory layer on said memory level, said bottom electrode comprising an upper highly-conductive sub-layer and a lower semi-conductive sub-layer;

2) applying a photo-resist layer and forming a hole therein at the location of said decoding device;

3) etching said memory layer and said upper highly-conductive sub-layer up to said lower semi-conductive sub-layer under said hole, then removing said photo-resist layer;

4) etching said memory layer and said bottom electrode to define at least a x-line;

5) depositing and etching a highly-conductive material to define at least a y-line and a control-line (c-line);

wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

8. The method according to claim 7, wherein the overlap portion and the non-overlap portions of said x-line with said y-line are both highly-conductive.

9. The method according to claim 7, wherein the bottom electrode of said memory device comprises both said upper highly-conductive sub-layer and said lower semi-conductive sub-layer.

10. The method according to claim 7, wherein said memory device is a two-terminal device.

11. The method according to claim 7, wherein the overlap portion of said x-line with said c-line is semi-conductive;

and, the non-overlap portions of said x-line with said c-line are highly-conductive.

14. The method according to claim 7, wherein the bottom electrode of said decoding device comprises only said lower semi-conductive sub-layer.

15. A manufacturing method of a JFET-type compact three-dimensional memory (3D-M_C) including a decoding device and a memory device on a memory level above a semiconductor substrate, comprising the steps of:

1) forming a bottom electrode comprising a metallic material and a memory layer on said memory level;

2) applying a photo-resist layer and forming a hole therein at the location of said decoding device;

3) etching said memory layer and said highly-conductive material under said hole;

removing said photo-resist layer; and

, filling said hole with a semi-conductive material;

4) etching said memory layer and said bottom electrode to define at least a x-line;

5) depositing and etching a high-conductive material to define at least a y-line and a control-line (c-line);

wherein said memory device is formed at the intersection of said x-line and said y-line, and said decoding device is formed at the intersection of said x-line and said c-line.

16. The method according to claim 15, wherein the overlap portion and the non-overlap portions of said x-line with said y-line are both highly-conductive.

17. The method according to claim 15, wherein said memory device is a two-terminal device.

18. The method according to claim 15, wherein

the overlap portion of said x-line with said c-line is semi-conductive;

and,

the non-overlap portions of said x-line with said c-line are highly-conductive.

19. The method according to claim 15, wherein said decoding device is a three-terminal device.

20. The method according to claim 15, wherein said decoding device comprises a pass-transistor.