Method and device for metal gate stacks

• US 10,211,309 B2
• Filed: 09/21/2016
• Issued: 02/19/2019
• Est. Priority Date: 10/19/2015
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US15/272,197
• Publication Number:
  US 20170110553A1
• Time in Patent Office: 881 Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a high-k dielectric layer on the substrate, a capping layer on the high-k dielectric layer, forming a first N-type work function metal layer on the capping layer, forming a second N-type work function metal layer on the first N-type work function metal layer, and forming a metal electrode layer on the second N-type work function metal layer. The second N-type work function metal layer has a Ti/Al atomic ratio greater than the Ti/Al atomic ratio of the first N-type work function metal layer. The second work function metal layer having a higher Ti/Al atomic ratio will not absorb appreciable oxygen from the atmosphere, so that oxygen will not be available to the first work function metal layer, thereby reducing the oxidation level of the first work function metal layer.

Claims

1. A semiconductor device comprising:

a substrate;

a high-k dielectric layer on the substrate;

a first homogenous capping layer directly on the high-k dielectric layer;

a first N-type work function metal layer directly on the first capping layer;

a second N-type work function metal layer on the first N-type work function metal layer; and

a metal electrode layer on the second N-type work function metal layer,

wherein a Ti/Al atomic ratio of the second N-type work function metal layer is greater than a Ti/Al atomic ratio of the first N-type work function metal layer.

2. The semiconductor device of claim 1, wherein the first capping layer and the first N-type work function metal layer are formed in a same station.

3. The semiconductor device of claim 1, wherein:

the first capping layer comprises TiN or TiSiN.

4. The semiconductor device of claim 1, further comprising an interface layer disposed between the substrate and the high-k dielectric layer.

5. The semiconductor device of claim 1, further comprising an adhesion layer disposed between the second N-type work function metal layer and the metal electrode layer.

6. The semiconductor device of claim 1, further comprising:

a first trench and a second trench separated from each other by an interlayer dielectric layer;

wherein the first trench comprises;

the high-k dielectric layer on the substrate;

the first capping layer on the high-k dielectric layer;

the first N-type work function metal layer on the capping layer;

the second N-type work function metal layer on the first N-type work function metal layer; and

the metal electrode layer on the second N-type work function metal layer.

7. The semiconductor device of claim 6, wherein the first trench is disposed in an NMOS region, and the second trench is disposed in a PMOS region.

8. The semiconductor device of claim 6, wherein the second trench comprises:

the high-k dielectric layer on the substrate;

a second capping layer on the high-k dielectric layer;

a barrier layer on the capping layer;

a P-type work function metal layer on the barrier layer;

the first capping layer on the P-type work function metal layer;

the first N-type work function metal layer on the first capping layer;

the second N-type work function metal layer on the first N-type work function metal layer; and

the metal electrode layer on the second N-type work function metal layer.

9. The semiconductor device of claim 8, wherein the barrier layer comprises TaN.

10. The semiconductor device of claim 8, wherein the P-type work function metal layer comprises Ti_xN_y, x representing a ratio of atoms of Ti, and y representing a ratio of atoms of N.

11. The semiconductor device of claim 8, wherein the P-type work function metal layer comprises TaN or TaC.

12. The semiconductor device of claim 1, wherein the first N-type work function metal layer comprises TiAl, TiCAl, TiNAl, or TiSiAl.

13. The semiconductor device of claim 1, wherein the second N-type work function metal layer comprises Ti_xAl_y, Ti_xC_zAl_y, Ti_xN_zAl_y, or Ti_xSi_zAl_y, x representing a ratio of atoms of Ti, y representing a ratio of atoms of Al, z representing a ratio of atoms of the corresponding C, N, and Si, and x being greater than y.

14. The semiconductor device of claim 1, wherein the metal electrode layer comprises W or Al.