Semiconductor modification process for conductive and modified electrical regions and related structures

• US 10,211,371 B2
• Filed: 02/13/2015
• Issued: 02/19/2019
• Est. Priority Date: 02/13/2014
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Facebook Technologies, LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Bonar, James Ronald, Valentine, Gareth, Gorton, Stephen Warren, Gong, Zheng, Small, James
• Primary Examiner(s): Moore, Whitney
• Application Number:
  US15/118,684
• Publication Number:
  US 20170047481A1
• Time in Patent Office: 1,467 Days
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01S 3/005 Optical devices external to the laser cavity, specially adapted for lasers, e.g. for homogenisation of the beam or for manipulating laser pulses, e.g. pulse shaping shaping laser beam for working metal or other materials B23K26/06; optical elements, systems or apparatus in general G02B
• CPC Class Codes: H01S 5/00 Semiconductor lasers superluminescent diodes H01L33/00
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/04253 having specific optical properties, e.g. transparent electrodes
• CPC Class Codes: H01S 5/04257 having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/18308 having a special structure for lateral current or light confinement
• CPC Class Codes: H01S 5/18341 Intra-cavity contacts
• CPC Class Codes: H01S 5/2068 obtained by radiation treatment or annealing
• CPC Class Codes: H01S 5/2086 lateral etch control, e.g. mask induced
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

There is herein described a process for providing improved device performance and fabrication techniques for semiconductors. More particularly, the present invention relates to a process for forming features, such as pixels, on GaN semiconductors using a p-GaN modification and annealing process. The process also relates to a plasma and thermal anneal process which results in a p-GaN modified layer where the annealing simultaneously enables the formation of conductive p-GaN and modified p-GaN regions that behave in an n-like manner and block vertical current flow. The process also extends to Resonant-Cavity Light Emitting Diodes (RCLEDs), pixels with a variety of sizes and electrically insulating planar layer for electrical tracks and bond pads.

Claims

1. A fabrication process for electronic components, comprising:

depositing a spreading layer on top of a GaN p-layer;

depositing a mask feature onto the spreading layer to form a structure with at least part of the structure protected by the mask feature, and at least another part of the structure not protected by the mask feature to form an unprotected mask region; and

processing the unprotected mask region to form an area with modified electrical characteristics from the GaN p-layer, wherein the processing includes;

exposing the structure having the mask feature to a plasma treatment;

removing the mask feature from the structure after exposing the structure to the plasma treatment and prior to annealing the plasma treated structure; and

annealing the plasma treated structure, wherein;

the at least other part of the structure not protected by the mask feature is exposed to the plasma treatment and forms a modified p-GaN region that blocks current flow due to the plasma treatment and annealing process; and

the at least part of the structure protected by the mask is shielded from the plasma treatment and forms a conductive contact after the annealing.

2. The fabrication process for electronic components according to claim 1, wherein the processing of the unprotected mask region causes a reversal in the effective doping of the at least other part of the structure to behave as n-doped GaN.

3. The fabrication process for electronic components according to claim 1, wherein exposing the structure to the plasma treatment, causes the at least other part of the structure protected by the mask feature to be shielded from the plasma treatment and remain unmodified p-GaN.

4. The fabrication process for electronic components according to claim 3, wherein annealing the structure results in the unmodified p-GaN forming the modified p-GaN regions.

5. The fabrication process for electronic components according to claim 1, wherein the processed structure is one of:

aRCLED;

aVCSEL;

astructure with small planar pixels;

a semiconductor a structure with patterned p-contacts; and

a structure with current blocking regions.

6. The fabrication process according to claim 1, further comprising forming a mesa in the GaN p-layer with a planar active area within the mesa using lithography.

7. The fabrication process for electronic components according to claim 1,

wherein the spreading layer has a thickness of about 20 nm.

8. The fabrication process according to claim 1, wherein the annealed structure is one of:

a RCLED;

a VCSEL;

a structure with small planar pixels;

a semiconductor;

a structure with patterned/graded p-contact resistance; and

a structure with electrical isolation.

9. The fabrication process according to claim 1, wherein Resonant Cavity LEDs (RCLEDs) are formed and wherein a GaN modified planar region is capable of being fabricated to a high resolution and thus create a well-defined cavity diameter (aperture).

10. The fabrication process according to claim 1, wherein Vertical Cavity Surface Emitting Lasers (VCSELs) are formed and wherein GaN modification provides a route to maintaining a low-loss planar high reflectivity DBR mirror above the p-GaN material whilst allowing the current to be precisely channeled into the required active region.

11. The fabrication process according to claim 1, further comprising forming microlens structures, scattering structures, diffractive optical elements, or photonic crystals on a light emitting surface of a microLED device.

12. A fabrication process for electronic components comprising the following steps:

depositing a spreading layer on top of a GAN p-layer;

depositing a mask feature onto the spreading layer to form a structure with at least part of the structure protected by the mask feature and at least another part of the structure not protected by the mask feature;

exposing the structure including the mask feature to a plasma treatment;

removing the mask from the structure after exposing the structure to the plasma treatment and prior to annealing the plasma treated structure; and

annealing the plasma treated structure;

wherein the at least other part of the structure not protected by the mask feature is exposed to the plasma treatment and forms a modified p-GaN region that behaves in an n-like manner and blocks current flow due to the plasma treatment and annealing process and the at least part of the structure protected by the mask are shielded from the plasma treatment and forms a conductive contact after annealing.

13. The fabrication process according to claim 12, wherein the annealed structure includes at least one of:

a CLED;

a VCSEL;

a structure with small planar pixels;

a semiconductor;

a structures with graded/patterned p-contact resistance; and

a structure with electrical isolation.

14. The fabrication process according to claim 12, wherein the spreading layer has a thickness of about 20 nm on top of the GaN p-layer.

15. The fabrication process according to claim 12, wherein the structure formed includes any of the following:

a RCLED;

a VCSEL;

a structure with small planar pixels;

a semiconductor;

a structure with patterned/graded p-contact resistance; and

a structure with modified p-regions that behave in an n-like manner and block current flow.

16. Modified structures formed by a process comprising the following steps:

depositing a spreading layer on top of a GaN p-layer to form a structure;

depositing a mask feature onto the structure with at least a part of the structure are protected by the mask feature and at least another part of the structure not protected by the mask feature;

exposing the structure to a plasma treatment;

removing the mask from the structure after exposing the structure to the plasma treatment and prior to annealing the plasma treated structure; and

annealing the plasma treated structure;

wherein the at least another part of the structure not protected by the mask feature is exposed to the plasma treatment and forms a modified p-region that behaves in an n-like manner and blocks current flow due to the plasma treatment and annealing process and the at least part of the structure protected by the mask feature are shielded from the plasma treatment and forms an ohmic contact after annealing.

17. The modified structures according to claim 16, wherein the structures formed include any of the following:

RCLEDs;

VCSELs;

structures with small planar pixels;

semiconductors;

structures with patterned/graded p-contact resistance and structures with modified p-regions that behave in an n-like manner and block current flow.