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Semiconductor modification process for conductive and modified electrical regions and related structures

  • US 10,211,371 B2
  • Filed: 02/13/2015
  • Issued: 02/19/2019
  • Est. Priority Date: 02/13/2014
  • Status: Active Grant
First Claim
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1. A fabrication process for electronic components, comprising:

  • depositing a spreading layer on top of a GaN p-layer;

    depositing a mask feature onto the spreading layer to form a structure with at least part of the structure protected by the mask feature, and at least another part of the structure not protected by the mask feature to form an unprotected mask region; and

    processing the unprotected mask region to form an area with modified electrical characteristics from the GaN p-layer, wherein the processing includes;

    exposing the structure having the mask feature to a plasma treatment;

    removing the mask feature from the structure after exposing the structure to the plasma treatment and prior to annealing the plasma treated structure; and

    annealing the plasma treated structure, wherein;

    the at least other part of the structure not protected by the mask feature is exposed to the plasma treatment and forms a modified p-GaN region that blocks current flow due to the plasma treatment and annealing process; and

    the at least part of the structure protected by the mask is shielded from the plasma treatment and forms a conductive contact after the annealing.

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