Inverter capacitor with phase-out bus bar

• US 10,211,755 B1
• Filed: 04/12/2018
• Issued: 02/19/2019
• Est. Priority Date: 08/11/2017
• Status: Active Grant

• Current Assignee: GalaTech, Inc.
• Original Assignee: GalaTech, Inc.
• Inventors: Liu, Wenjun, Ramm, Robert James
• Primary Examiner(s): Nguyen, Matthew
• Application Number:
  US15/952,144
• Publication Number:
  US 20190052188A1
• Time in Patent Office: 313 Days
• CPC Class Codes: H02M 1/0048 Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/143 using compensating arrangements for reducing noise from the supply in transmission systems H04B15/005
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

Claims

1. An inverter component, comprising:

a case;

a capacitor situated in the case, the capacitor having a first terminal and a second terminal;

a first bus bar configured to electrically couple the first terminal of the capacitor to a first transistor external to the case, the first bus bar comprising a first portion situated in the case and a second portion extending from the case to contact the first transistor;

a second bus bar configured to electrically couple the second terminal of the capacitor to a second transistor external to the case, the second bus bar comprising a first portion situated in the case and a second portion extending from the case to contact the second transistor; and

a phase-out bus bar configured to electrically couple the first transistor to the second transistor, the phase-out bus bar comprising a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.

2. The inverter component of claim 1, wherein the first portion of the phase-out bus bar comprises a conductive sheet situated above the capacitor in the case.

3. The inverter component of claim 2, wherein:

the first terminal of the capacitor is on the bottom of the capacitor;

the first portion of the first bus bar comprises a conductive sheet situated below the capacitor in the case;

the second terminal of the capacitor is on the top of the capacitor; and

the first portion of the second bus bar comprises a conductive sheet situated above the capacitor and below the first portion of the phase-out bus bar in the case.

4. The inverter component of claim 3, wherein:

the first terminal of the capacitor is a positive terminal; and

the second terminal of the capacitor is a negative terminal.

5. The inverter component of claim 1, wherein:

the case is sealed; and

the capacitor, the first portions of the first bus bar, second bus bar, and phase-out bus bar are in the case.

6. The inverter component of claim 5, wherein the case is sealed with epoxy.

7. The inverter component of claim 1, wherein:

the first bus bar couples a collector of the first transistor to the first terminal of the capacitor;

the phase-out bus bar couples an emitter of the first transistor to the collector of the second transistor; and

the second bus bar couples an emitter of the second transistor to the second terminal of the capacitor.

8. The inverter component of claim 1, wherein:

the first bus bar couples a first source/drain terminal of the first transistor to the first terminal of the capacitor;

the phase-out bus bar couples the second source/drain terminal of the first transistor to a first source/drain terminal of the second transistor; and

the second bus bar couples the second source/drain terminal of the second transistor to the second terminal of the capacitor.

9. The inverter component of claim 1, wherein the phase-out bus bar is a first phase-out bus bar to provide a first phase of alternating current, the inverter component further comprising:

a second phase-out bus bar, distinct from the second bus bar, configured to electrically couple a third transistor external to the case to a fourth transistor external to the case and to provide a second phase of alternating current, the second phase-out bus bar comprising a first portion situated in the case, a second portion extending from the case to contact the third transistor, and a third portion extending from the case to contact the fourth transistor.

10. The inverter component of claim 9, further comprising:

a third phase-out bus bar configured to electrically couple a fifth transistor external to the case to a sixth transistor external to the case and to provide a third phase of alternating current, the third phase-out bus bar comprising a first portion situated in the case, a second portion extending from the case to contact the fifth transistor, and a third portion extending from the case to contact the sixth transistor.

11. The inverter component of claim 10, wherein the first portions of the first, second, and third phase-out bus bars comprise respective first, second, and third conductive sheets situated above the capacitor in the case and arranged in a line.

12. The inverter component of claim 11, wherein:

the first terminal of the capacitor is on the bottom of the capacitor;

the first portion of the first bus bar comprises a conductive sheet situated below the capacitor in the case;

the second terminal of the capacitor is on the top of the capacitor; and

the first portion of the second bus bar comprises a conductive sheet situated above the capacitor and below the first, second, and third conductive sheets.

13. The inverter component of claim 1, wherein:

the first bus bar is configured to electrically couple the first terminal of the capacitor to a first plurality of transistors external to the case and comprises a plurality of portions extending from the case to contact respective transistors of the first plurality of transistors;

the second bus bar is configured to electrically couple the second terminal of the capacitor to a second plurality of transistors external to the case and comprises a plurality of portions extending from the case to contact respective transistors of the second plurality of transistors; and

the phase-out bus bar is configured to electrically couple the first plurality of transistors to the second plurality of transistors and comprises a first plurality of portions extending from the case to contact respective transistors of the first plurality of transistors and a second plurality of portions extending from the case to contact respective transistors of the second plurality of transistors.

14. The inverter component of claim 13, wherein the phase-out bus-bar is a first phase-out bus bar to provide a first phase of alternating current, the inverter component further comprising:

a second phase-out bus bar configured to electrically couple a third plurality of transistors to a fourth plurality of transistors and to provide a second phase of alternating current, the second phase-out bus bar comprising a portion situated in the case and a plurality of portions extending from the case to contact respective transistors of the third and fourth pluralities of transistors;

a third phase-out bus bar configured to electrically couple a fifth plurality of transistors to a sixth plurality of transistors and to provide a third phase of alternating current, the third phase-out bus bar comprising a portion situated in the case and a plurality of portions extending from the case to contact respective transistors of the fifth and sixth pluralities of transistors;

wherein;

the first bus bar is configured to electrically couple the first terminal of the capacitor to the third and fifth pluralities of transistors and comprises a plurality of portions extending from the case to contact respective transistors of the third and fifth pluralities of transistors; and

the second bus bar is configured to electrically couple the second terminal of the capacitor to the fourth and sixth pluralities of transistors and comprises a plurality of portions extending from the case to contact respective transistors of the fourth and sixth pluralities of transistors.

15. An inverter component, comprising:

a sealed case;

a capacitor sealed in the case, the capacitor having a first terminal and a second terminal;

a first bus bar configured to electrically couple the first terminal of the capacitor to a first plurality of transistors, the first bus bar comprising a first portion sealed in the case and respective portions extending from the case to contact respective transistors of the first plurality of transistors;

a second bus bar configured to electrically couple the second terminal of the capacitor to a second plurality of transistors, the second bus bar comprising a first portion sealed in the case and respective portions extending from the case to contact respective transistors of the second plurality of transistors; and

a plurality of phase-out bus bars configured to electrically couple respective subsets of the first plurality of transistors to respective subsets of the second plurality of transistors, each phase-out bus bar of the plurality of phase-out bars comprising a portion sealed in the case and respective portions extending from the case to contact respective transistors of the first and second pluralities of transistors.