Inverter capacitor with phase-out bus bar
First Claim
1. An inverter component, comprising:
- a case;
a capacitor situated in the case, the capacitor having a first terminal and a second terminal;
a first bus bar configured to electrically couple the first terminal of the capacitor to a first transistor external to the case, the first bus bar comprising a first portion situated in the case and a second portion extending from the case to contact the first transistor;
a second bus bar configured to electrically couple the second terminal of the capacitor to a second transistor external to the case, the second bus bar comprising a first portion situated in the case and a second portion extending from the case to contact the second transistor; and
a phase-out bus bar configured to electrically couple the first transistor to the second transistor, the phase-out bus bar comprising a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.
2 Assignments
0 Petitions
Accused Products
Abstract
The various implementations described herein include inverter devices and systems. In one aspect, an inverter includes: a case; a capacitor within the case having a first terminal and a second terminal; a first bus bar including a first portion within the case and a second portion extending from the case to contact a first transistor; a second bus bar including a first portion situated in the case and a second portion extending from the case to contact a second transistor; and a phase-out bus bar including a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor.
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Citations
15 Claims
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1. An inverter component, comprising:
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a case; a capacitor situated in the case, the capacitor having a first terminal and a second terminal; a first bus bar configured to electrically couple the first terminal of the capacitor to a first transistor external to the case, the first bus bar comprising a first portion situated in the case and a second portion extending from the case to contact the first transistor; a second bus bar configured to electrically couple the second terminal of the capacitor to a second transistor external to the case, the second bus bar comprising a first portion situated in the case and a second portion extending from the case to contact the second transistor; and a phase-out bus bar configured to electrically couple the first transistor to the second transistor, the phase-out bus bar comprising a first portion situated in the case, a second portion extending from the case to contact the first transistor, and a third portion extending from the case to contact the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An inverter component, comprising:
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a sealed case; a capacitor sealed in the case, the capacitor having a first terminal and a second terminal; a first bus bar configured to electrically couple the first terminal of the capacitor to a first plurality of transistors, the first bus bar comprising a first portion sealed in the case and respective portions extending from the case to contact respective transistors of the first plurality of transistors; a second bus bar configured to electrically couple the second terminal of the capacitor to a second plurality of transistors, the second bus bar comprising a first portion sealed in the case and respective portions extending from the case to contact respective transistors of the second plurality of transistors; and a plurality of phase-out bus bars configured to electrically couple respective subsets of the first plurality of transistors to respective subsets of the second plurality of transistors, each phase-out bus bar of the plurality of phase-out bars comprising a portion sealed in the case and respective portions extending from the case to contact respective transistors of the first and second pluralities of transistors.
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Specification