Complementary current field-effect transistor devices and amplifiers

• US 10,211,781 B2
• Filed: 07/29/2015
• Issued: 02/19/2019
• Est. Priority Date: 07/29/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: Schober, Robert C., Schober, Susan Marya
• Primary Examiner(s): Choe, Henry
• Application Number:
  US15/748,305
• Publication Number:
  US 20180219514A1
• Time in Patent Office: 1,301 Days
• Field of Search: 330277, 330307, 330311, 330 66
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/72 the amplifier stage being a common gate configuration MOSFET
• CPC Class Codes: H03F 3/16 with field-effect devices
• CPC Class Codes: H03K 19/018564 with at least one differential stage H03K19/018578 takes precedence
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

Claims

1. A solid-state device comprising:

a. first and second complementary field effect transistors, each comprising a source and a drain, wherein the source and drain of the first transistor define a first channel and the source and drain of the second transistor define a second channel;

b. a first diffusion (first iPort) that divides the first channel into a first source channel segment between the source and the first iPort and a first drain channel segment between the first iPort and the drain, and a second diffusion (second iPort) that divides the second channel into a second source channel segment between the source and the second iPort and a second drain channel segment between the second iPort and the drain;

c. a common gate port coupled to the first source channel segment, the first drain channel segment, the second source channel segment and the second drain channel segment; and

d. a common drain port electrically connected to the drains of the first and second transistors.

2. A solid-state device as in claim 1 wherein the device further comprises a voltage source connected to the common gate port and is operative to provide a voltage output at the common drain port.

3. A solid-state device as in claim 1 wherein the device further comprises a current source connected to at least one of the first and second iPorts and is operative to provide a current output at the common drain port.

4. A solid-state device as in claim 1 wherein the device further comprises a voltage source connected to the common gate port and is operative to provide a current output at the common drain port.

5. A solid-state device as in claim 1 wherein the device further comprises a current source connected to at least one of the first and second iPorts and is operative to provide a voltage output at the common drain port.

6. A solid-state device as in claim 1 wherein the device further comprises a current source connected to at least one of the first and second iPorts and a voltage source connected to the common gate port, and is operative to provide a voltage output at the common drain port.

7. A solid-state device as in claim 1 wherein the device further comprises a current source connected to at least one of the first and second iPorts and a voltage source connected to the common gate port, and is operative to provide a current output at the common drain port.

8. A solid-state device as in claim 7 wherein the device is operative to also provide a simultaneous voltage output at the common drain port.

9. A solid-state device as in claim 1 wherein a ratio of a width and a length of each of the first source channel segment, the first drain channel segment, the second source channel segment and the second drain channel segment is adjusted for one or more of impedance matching, gain, noise, and power consumption.