Low-power wide-swing sense amplifier with dynamic output stage biasing

• US 10,211,782 B1
• Filed: 10/16/2017
• Issued: 02/19/2019
• Est. Priority Date: 10/16/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Banerjee, Anirban, Rasmus, Todd Morgan
• Primary Examiner(s): Hiltunen, Thomas J.
• Application Number:
  US15/785,294
• Time in Patent Office: 491 Days
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2203/45112 the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45626 the LC comprising biasing means controlled by the input signal
• CPC Class Codes: H03F 2203/45646 the LC comprising an extra current source
• CPC Class Codes: H03F 2203/45658 the LC comprising two diodes of current mirrors
• CPC Class Codes: H03F 2203/45661 the LC comprising one or more controlled floating gates
• CPC Class Codes: H03F 2203/45726 the LC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45273 Mirror types
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses

Abstract

A rail-to-rail sense amplifier includes a PMOS differential pair and an NMOS differential pair that are arranged in parallel with regard to a biasing network for driving a class AB output stage. The sense amplifier includes a first current differential amplifier and a second current differential amplifier for increasing the output swing while reducing power consumption.

Claims

1. A sense amplifier, comprising:

a p-channel metal-oxide semiconductor (PMOS) differential pair of transistors configured to respond to a differential input voltage;

an n-channel metal-oxide semiconductor (NMOS) differential pair of transistors configured to respond to the differential input voltage;

an output stage including a PMOS output transistor and an NMOS output transistor;

a first current differential amplifier configured to sink a first difference current proportional to a difference between a first current for a first NMOS transistor in the NMOS differential pair of transistors and a second current for a second NMOS transistor in the NMOS differential pair of transistors to discharge a gate voltage for the PMOS output transistor;

a biasing network configured to discharge the gate voltage for the NMOS output transistor responsive to a sum of the first current and a third current in a first PMOS transistor in the PMOS differential pair of transistors;

a first NMOS switch transistor and

a second NMOS switch transistor wherein the differential input voltage is coupled across a pair of gates for the first NMOS switch transistor and the second NMOS switch transistor, and wherein the first NMOS switch transistor and the second NMOS switch transistor are coupled in parallel between the first current differential amplifier and the gate of the PMOS output transistor.

2. The sense amplifier of claim 1, further comprising:

a second current differential amplifier configured to source a second difference current proportional to a difference between a fourth current for a second PMOS transistor in the PMOS differential pair of transistors and the third current to charge a gate for the NMOS output transistor, wherein the biasing network is further configured to charge the gate of the PMOS output transistor responsive to a sum of the fourth current and the second current.

3. The sense amplifier of claim 2, further comprising:

a first PMOS switch transistor; and

a second PMOS switch transistor, wherein the first PMOS switch transistor and the second PMOS switch transistor are configured to respond to the differential input voltage, and wherein the first PMOS switch transistor and the second PMOS switch transistor are coupled in parallel between the second current differential amplifier and the gate of the NMOS output transistor.

4. The sense amplifier of claim 1, further comprising:

a first current source configured to bias a pair of source terminals for the PMOS differential pair of transistors; and

a second current source configured to bias a pair of source terminals for the NMOS differential pair of transistors.

5. The sense amplifier of claim 2, wherein a positive half of the differential input voltage is a control voltage for a loop filter in a phase-locked loop (PLL), and wherein a negative half of the differential input voltage is a drain voltage for a transistor in a charge pump for the PLL.

6. The sense amplifier of claim 5, wherein a gate for the first NMOS transistor and a gate for the second PMOS transistor are both coupled to a node carrying the control voltage, and wherein a gate for the second NMOS transistor and a gate for the first PMOS transistor are both coupled to a drain for the transistor in the charge pump for the PLL.

7. The sense amplifier of claim 1, wherein the first differential current amplifier is configured to amplify the first difference current.

8. The sense amplifier of claim 2, wherein the second differential current amplifier is configured to amplify the second difference current.

9. A sense amplifier, comprising:

a p-channel metal-oxide semiconductor (PMOS) differential pair of transistors configured to respond to a differential input voltage;

an n-channel metal-oxide semiconductor (NMOS) differential pair of transistors configured to respond to the differential input voltage;

an output stage including a PMOS output transistor and an NMOS output transistor;

a first current differential amplifier configured to sink a first difference current proportional to a difference between a first current for a first NMOS transistor in the NMOS differential pair of transistors and a second current for a second NMOS transistor in the NMOS differential pair of transistors to discharge a gate voltage for the PMOS output transistor; and

a biasing network configured to discharge the gate voltage for the NMOS output transistor responsive to a sum of the first current and a third current in a first PMOS transistor in the PMOS differential pair of transistors,

wherein the biasing network comprises a first bias NMOS transistor and a second bias PMOS transistor coupled in parallel between a gate of the PMOS output transistor and a gate of the NMOS output transistor.

10. The sense amplifier of claim 9, wherein a gate for the first bias NMOS transistor is configured to receive a first bias voltage and a wherein a gate of the second bias PMOS transistor is configured to receive a second bias voltage.

11. A method of driving an output voltage from a sense amplifier, comprising:

while a common mode voltage for a differential input voltage is above a first threshold voltage;

driving a pair of gates for a differential pair of p-channel metal-oxide semiconductor (PMOS) transistors with the differential input voltage to substantially shut off a first current in a first one of the PMOS transistors and to substantially shut off a second current in a second one of PMOS transistors;

driving a pair of gates for a differential pair of n-channel metal-oxide semiconductor (NMOS) transistors with the differential input voltage to conduct a third current in a first one of NMOS transistors and to conduct a fourth current in a second one of the NMOS transistors;

sinking a current proportional to a sum of the second current and the third current from a gate of an NMOS output transistor to partially discharge the gate of the NMOS output transistor, wherein the partially discharging of the gate of the NMOS output transistor also partially discharges a gate of a PMOS output transistor through a biasing network;

sinking a first difference current proportional to a difference between the third current and the fourth current from the gate of the PMOS output transistor to further discharge the gate of the PMOS output transistor, wherein the further discharging of the gate of the PMOS output transistor also further discharges the gate of the NMOS output transistor through the biasing network; and

while the common mode voltage for a differential input voltage is below a second threshold;

driving the pair of gates for the differential pair of PMOS transistors with the differential input voltage to conduct the first current in the first one of the PMOS transistors and to conduct the second current in the second one of PMOS transistors;

driving the pair of gates for a differential pair of NMOS transistors with the differential input voltage to substantially shut off the third current in the first one of NMOS transistors and to substantially shut off the fourth current in the second one of the NMOS transistors;

sourcing a current proportional to a sum of the first current and the fourth current into the gate of the PMOS output transistor to charge the gate of the PMOS output transistor towards the supply voltage, wherein the charging of the gate of the PMOS output transistor also charges the gate of the NMOS output transistor towards the supply voltage through the biasing network; and

sourcing a second difference current proportional to a difference between the first current and the second current to the gate of the NMOS output transistor to further charge the gate of the NMOS output transistor, wherein the further charging of the gate of the NMOS output transistor also further charges the gate of the PMOS output transistor through the biasing network.

12. The method of claim 11, further comprising:

switching on a first pair of switch transistors to sink the first difference current from the gate of the PMOS output transistor.

13. The method of claim 11, further comprising:

switching on a second pair of switch transistors to source the second difference current to the gate of the NMOS output transistor.

14. The method of claim 11, wherein the first difference current is a multiple of the difference between the third current and the fourth current.

15. A sense amplifier, comprising:

a p-channel metal-oxide semiconductor (PMOS) differential pair of transistors configured to respond to a differential input voltage;

an n-channel metal-oxide semiconductor (NMOS) differential pair of transistors configured to respond to the differential input voltage;

an output stage including a PMOS output transistor and an NMOS output transistor;

a first current differential amplifier configured to sink a first difference current proportional to a difference between a first current for a first NMOS transistor in the NMOS differential pair of transistors and a second current for a second NMOS transistor in the NMOS differential pair of transistor to discharge a gate voltage for the PMOS output transistor;

means for biasing the gate voltage for the NMOS output transistor responsive to a sum of the first current and a third current in a first PMOS transistor in the PMOS differential pair and for biasing a gate voltage for the PMOS output transistor responsive to a sum of a fourth current in a second PMOS transistor in the PMOS differential pair and the second current; and

a second current differential amplifier configured to source a second difference current proportional to a difference between the fourth current and the third current to charge the gate voltage for the NMOS output transistor.

16. The sense amplifier of claim 15, wherein the sense amplifier is integrated within a charge pump to mitigate charge sharing for a phase-locked loop.

17. The sense amplifier of claim 15, further comprising:

a first current source configured to bias a pair of source terminals for the PMOS differential pair of transistors; and

a second current source configured to bias a pair of source terminals for the NMOS differential pair of transistors.