PHEMT components with enhanced linearity performance
First Claim
1. A pseudomorphic high electron mobility transistor circuit comprising:
- at least one pseudomorphic high electron mobility transistor connected between an input signal terminal and a load, the at least one pseudomorphic high electron mobility transistor configured to produce a first harmonic signal at the load responsive to being driven by an input signal of a fundamental frequency received at the input signal terminal, the first harmonic signal having a first phase; and
at least one non-linear resistor connected to the at least one pseudomorphic high electron mobility transistor and having a resistance value selected to produce a second harmonic signal at the load, the second harmonic signal having a second phase opposite to the first phase.
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Abstract
pHEMT-based circuits and methods of improving the linearity thereof. One example pHEMT circuit includes a pHEMT connected between an input terminal and a load and a non-linear resistance connected to the pHEMT. The pHEMT produces a first harmonic signal at the load responsive to being driven by an input signal of a fundamental frequency received at the input terminal, the first harmonic signal having a first phase. The non-linear resistance has a resistance selected to produce a second harmonic signal at the load having a second phase opposite to the first phase. Methods can include determining a first amplitude and a first phase of a first harmonic signal produced at the load by a pHEMT in an ON state, and tuning the non-linear resistance to produce at the load a second harmonic signal having a second amplitude and a second phase that minimizes a net harmonic signal at the load.
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Citations
20 Claims
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1. A pseudomorphic high electron mobility transistor circuit comprising:
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at least one pseudomorphic high electron mobility transistor connected between an input signal terminal and a load, the at least one pseudomorphic high electron mobility transistor configured to produce a first harmonic signal at the load responsive to being driven by an input signal of a fundamental frequency received at the input signal terminal, the first harmonic signal having a first phase; and at least one non-linear resistor connected to the at least one pseudomorphic high electron mobility transistor and having a resistance value selected to produce a second harmonic signal at the load, the second harmonic signal having a second phase opposite to the first phase. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of improving linearity in a pseudomorphic high electron mobility transistor circuit, the method comprising:
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driving a pseudomorphic high electron mobility transistor in an ON state with an input signal having a fundamental frequency; determining a first amplitude and a first phase of a first harmonic signal produced at a load by the pseudomorphic high electron mobility transistor in the ON state; and tuning a non-linear resistance connected to the pseudomorphic high electron mobility transistor to produce at the load a second harmonic signal having a second amplitude and a second phase that is opposite to the first phase so as to minimize a net harmonic signal at the load, the net harmonic signal corresponding to a sum of the first harmonic signal and the second harmonic signal, the first and second harmonic signals corresponding to third harmonics of the fundamental frequency. - View Dependent Claims (15, 16, 17)
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18. A method of improving linearity in a pseudomorphic high electron mobility transistor switch, the method comprising:
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determining a first amplitude and a first phase of a first harmonic signal produced at a load by the pseudomorphic high electron mobility transistor switch in an ON state; and tuning a gate resistance connected to a gate of the pseudomorphic high electron mobility transistor switch to produce a second harmonic signal at the load, the second harmonic signal having a second amplitude and a second phase that is opposite to the first phase such that a net harmonic signal at the load corresponding to a sum of the first harmonic signal and the second harmonic signal has a power level of less than −
50 dBm. - View Dependent Claims (19, 20)
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Specification