Voltage and frequency balancing at nominal point

• US 10,216,252 B2
• Filed: 04/13/2018
• Issued: 02/26/2019
• Est. Priority Date: 10/06/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Foreman, Eric A., Shuma, Stephen G.
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US15/952,602
• Publication Number:
  US 20180210534A1
• Time in Patent Office: 319 Days
• Field of Search: 716108
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Claims

1. A computer system for determining voltage and frequency pairs, the computer system comprising:

one or more computer processors, one or more computer readable storage media, and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising;

program instructions to identify an integrated circuit design;

program instructions to identify a timing model associated with the identified integrated circuit design;

program instructions to identify at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design;

program instructions to receive a number n that defines the number of at least one alternate voltage within the voltage range;

program instructions to analyze the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range;

program instructions to perform a single statistical static timing analysis for the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range, wherein the single statistical static timing analysis calculates voltage sensitivity via finite differencing with respect to the identified timing model;

program instructions to create a canonical variability of frequency dependent tests, wherein the clock period and voltage are parameterized;

program instructions perform a multi-corner static timing analysis for the identified integrated circuit based on the received number n for each number n for the identified at least one alternate voltage within the voltage range;

program instructions to calculate a timing at a first voltage point and a timing second voltage point;

program instructions to calculate a sensitivity to voltage that is a difference between the timing at the first voltage point and the timing at a second voltage point;

program instructions calculate a nominal slack;

program instructions to calculate one or more clock periods based on the calculated nominal slack;

program instructions to solve a slack equation for a clock period;

program instructions to calculate the clock period for each number n by inserting each calculated voltage for each number n into the solved slack equation for the clock period;

program instructions to provide a report based on the calculated one or more clock periods;

program instructions to optimize a voltage and frequency pairing for a best power-performance balance, wherein the voltage and frequency pairing meets a maximum power and a minimum frequency; and

program instructions to manufacture an integrated circuit based upon an optimized integrated circuit design using the optimized voltage and frequency pairing.