Data rebuild on feedback from a queue in a non-volatile solid-state storage

• US 10,216,411 B2
• Filed: 10/04/2016
• Issued: 02/26/2019
• Est. Priority Date: 08/07/2014
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Davis, John D., Hayes, John, Kannan, Hari, Miladinovic, Nenad, Tan, Zhangxi
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US15/285,410
• Publication Number:
  US 20170024141A1
• Time in Patent Office: 875 Days
• Field of Search: 714773, 714770, 714767
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/373 with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes
• CPC Class Codes: H03M 13/3761 using code combining, i.e. using combining of codeword portions which may have been transmitted separately, e.g. Digital Fountain codes, Raptor codes or Luby Transform [LT] codes

Abstract

A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget.

Claims

1. A method of reading data in a storage system, performed by the storage system, comprising:

receiving a request to read a bit in a storage memory;

evaluating, using feedback from a plurality of operations queues coupled to the storage memory, a path to the bit in the storage memory, responsive to the request to read the bit; and

determining a value of the bit via an alternate path to the storage memory, responsive to the evaluating, the determining comprising reading at least one other bit via the alternate path, in the storage memory.

2. The method of claim 1, wherein the evaluating comprises:

determining whether reading the bit via the path is within a targeted read time according to the feedback from the plurality of operations queues.

3. The method of claim 1, wherein the determining the value of the bit via the alternate path comprises determining a value of a redundant copy of the bit in the storage memory.

4. The method of claim 1, wherein the determining the value of the bit via the alternate path comprises reconstructing or rebuilding the bit.

5. The method of claim 1, wherein the feedback from the plurality of operations queues is regarding at least one of:

priority of operations in the operations queues, weighting of the operations, data read operations, data write operations, or erasure operations.

6. The method of claim 1, further comprising:

tagging operations in the operations queues; and

establishing a plurality of policies relative to the operations queues, wherein the evaluating is in accordance with the tagging and the policies.

7. A storage system, comprising:

storage memory;

a plurality of operations queues coupled to the storage memory;

at least one processor, configured to use feedback from the plurality of operations queues to evaluate a path to a bit in the storage memory, responsive to a request to read the bit; and

the at least one processor further configured to determine a value of the bit via an alternate path to the storage memory, responsive to a result of evaluating the path to the bit in the storage memory, and the at least one processor configured to reconstruct or rebuild the bit.

8. The storage system of claim 7, further comprising:

the at least one processor further configured to determine whether reading the bit via the path to the bit in the storage memory meets a targeted read time based on the feedback from the plurality of operations queues, wherein the result of the evaluating the path is that the reading the bit via the path does not meet the targeted read time.

9. The storage system of claim 7, wherein the at least one processor further configured to determine the value of the bit via the alternate path comprises:

the at least one processor configured to read a redundant copy of the bit in the storage memory, via the alternate path.

10. The storage system of claim 7, wherein the at least one processor configured to use the feedback from the plurality of operations queues comprises the at least one processor configured to use feedback regarding at least one of:

priority of operations in the operations queues, weighting of the operations in the operations queues, data read operations in the operations queues, data write operations in the operations queues, or erasure operations in the operations queues.

11. The storage system of claim 7, further comprising:

the at least one processor configured to tag operations in the operations queues and maintain a plurality of policies relating to the operations in the operations queues, wherein the result of the evaluating the path to the bit is based in part on such tags and policies.

12. The storage system of claim 7, wherein the at least one processor further configured to determine the value of the bit via the alternate path comprises:

the at least one processor further configured to read a plurality of bits in the storage memory other than the bit.

13. A storage system with solid-state storage memory, comprising:

a solid-state storage memory;

a plurality of operations queues, coupled via channels to the storage memory;

one or more processors configured to evaluate, using feedback from the plurality of operations queues, a path for reading a bit in the solid-state storage memory, in response to a request for a data or metadata read; and

the one or more processors configured to decide whether to read the bit via the path or via an alternate path, based on a result of such evaluation, wherein the plurality of operations queues are configured to provide, as feedback to the one or more processors, information regarding at least one of;

priority of operations in the operations queues, weighting of the operations, data read operations, data write operations, or erasure operations.

14. The storage system of claim 13, wherein:

the path comprises one of the channels to the storage memory, for reading the bit; and

the alternate path comprises another one of the channels to the storage memory, for reading a redundant copy of the bit.

15. The storage system of claim 13, wherein:

the path comprises one of the channels to the storage memory, for reading the bit; and

the alternate path comprises further channels to the storage memory, for reading further bits of an error correction code data stripe and reconstructing the bit.

16. The storage system of claim 13, further comprising:

the one or more processors configured to produce a corrected data segment, via the alternate path, including a reconstruction of the bit, without incurring latency penalty of reading the bit via the path, wherein the one or more processors decide to read the bit via the alternate path based on the feedback from the operations queues.

17. The storage system of claim 13, further comprising:

the one or more processors configured to read a redundant copy of the bit via the alternate path, without incurring latency penalty of reading the bit via the path, wherein the one or more processors decide to read the bit via the alternate path based on the feedback from the operations queues.