Methods and related devices for operating a memory array

• US 10,216,438 B2
• Filed: 11/30/2017
• Issued: 02/26/2019
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bedeschi, Ferdinando, Resta, Claudio, Ferraro, Marco
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US15/827,795
• Publication Number:
  US 20180095687A1
• Time in Patent Office: 453 Days
• Field of Search: 365163, 365189011, 36518915, 36518916, 36518909
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 13/02 using elements whose operation depends upon chemical change G11C13/0009 takes precedence
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Abstract

Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data hits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation and memory devices are also described.

Claims

1. A method of operating a memory array, the method comprising:

determining a pattern to be written to the memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored;

writing the pattern to the memory array;

providing a write password to the memory;

erasing the pattern from the memory array based on a determination that the write password is incorrect, and applying a set pulse to the memory array.

2. The method of claim 1, wherein the data bits having a state that is unimportant to the sensitive information to be stored are incorporated inside a same logic packet as the data bits having sensitive information to be stored.

3. The method of claim 2, wherein the logic packets are selected from at least one packet type including packet types of nibbles, bytes, words, double words, and long words.

4. The method of claim 1, further comprising defining a starting condition for each cell in the memory array prior to storing a plurality of bits in the memory array, the starting condition being defined by providing either one or more hard reset pulses or one or more soft reset pulses to each of the cells in the memory array.

5. The method of claim 4, further comprising programming the one or more hard reset pulses with a first pulse amplitude, and programming the one or more soft reset pulses with a second pulse amplitude that is different from the first pulse amplitude.

6. The method of claim 4, further comprising:

writing a logical “

0”

using the one or more hard reset pulses to one or more selected cells in the memory array; and

writing a logical “

1”

using the one or more soft reset pulses, to one or more remaining cells in the memory array.

7. The method of claim 1, further comprising executing two or more reset sequences on the memory array prior to writing the pattern to the memory array.

8. The method of claim 1, further comprising comparing the write password with information stored in a programmable memory to verify a validity of the write password.

9. The method of claim 1, wherein the method is for encrypting the memory array.

10. The method of claim 1, further comprising adjusting an internal read reference to maintain a margin for obtaining the pattern.

11. The method of claim 10, further comprising increasing current of the internal read reference to maintain the margin.

12. A device, comprising:

a memory array;

a processor coupled to the memory array to determine a pattern to be written to the memory array, the pattern comprising both data bits having sensitive information to be stored in the memory array and data bits having a state that is unimportant to the sensitive information to be stored in the memory array;

an internal state machine coupled to the memory array to write the pattern to the memory array; and

further comprising a command interface to receive and verify a read password, and compare the password with information stored in a programmable memory to verify a validity of the read password.

13. The device of claim 12, wherein the memory array comprises a number of phase-change memory (PCM) cells.

14. The device of claim 12, wherein the internal state machine is further to perform set and reset sequencing of the memory array.

15. A device to encrypt a memory array, the device comprising:

at least one type of memory including volatile memory types and non-volatile memory types in the memory array;

a processor coupled to the memory array to determine a pattern to be written to the memory array, the pattern comprising both data bits having sensitive information to be stored in the memory array and data bits having a state that is unimportant to the sensitive information to be stored in the memory array;

a write state machine coupled to the memory array to write the pattern to the memory array; and

further comprising a command interface to receive and verify a read password, and compare the password with information stored in a programmable memory to verify a validity of the read password.

16. The device of claim 15, further comprising at east one hardware-based core processor to handle baseband functions and perform application functions.