Method and apparatus for bus lock assistance

• US 10,216,650 B2
• Filed: 01/29/2018
• Issued: 02/26/2019
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chappell, Robert S., Faistl, John W., Gartler, Hermann W., Tucknott, Michael D., Parthasarathy, Rajesh S., Burns, David W.
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US15/883,021
• Publication Number:
  US 20180225228A1
• Time in Patent Office: 393 Days
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Claims

1. A method comprising:

detecting that a first instruction and a second instruction are locked instructions;

determining that execution of the first instruction and the second instruction each include imposing an initial bus lock; and

executing a bus lock assistance function in response to the determining, wherein the bus lock assistance function comprises;

preventing the initial bus lock from being imposed for the first instruction by raising a flag to cause execution of software including the first instruction to stop, and

permitting the initial bus lock to be imposed for the second instruction.

2. The method of claim 1, wherein the determining that the execution of the first instruction and the second instruction each includes imposing the initial bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not cacheable.

3. The method of claim 1, wherein the determining that the execution of the first instruction and the second instruction includes imposing the initial bus lock includes determining that a memory type of each of the first instruction and the second instruction does not permit a cache lock.

4. The method of claim 1, wherein the determining that the execution of the first instruction and the second instruction includes imposing the initial bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not within a cache.

5. The method of claim 1, wherein the determining that the execution of the first instruction and the second instruction includes imposing the initial bus lock includes determining that an address of a data item to be fetched by each of the first instruction and the second instruction crosses a cache line boundary.

6. The method of claim 1, wherein the bus lock assistance function further comprises preventing a bus lock protocol from being followed.

7. The method of claim 1, further comprising detecting that bus lock assistance has been enabled for the first instruction as a pre-condition to preventing the initial bus lock from being imposed for the first instruction, and detecting that bus lock assistance has been enabled for the second instruction as a pre-condition to permitting the initial bus lock to be imposed for the second instruction.

8. The method of claim 1, wherein the bus lock assistance function further comprises raising a second flag to indicate the initial bus lock is permitted for the second instruction.

9. An apparatus comprising:

instruction identification circuitry to identify when a first instruction and a second instruction are locked instructions;

first circuitry to determine if the first instruction and the second instruction are each to impose an initial bus lock when executed; and

second circuitry to trigger a bus lock assistance function when the first instruction and the second instruction are to each impose the initial bus lock when executed, wherein the bus lock assistance function is to;

prevent the initial bus lock from being imposed for the first instruction by raising a flag to cause execution of software including the first instruction to stop, and

permit the initial bus lock to be imposed for the second instruction.

10. The apparatus of claim 9, wherein at least the instruction identification circuitry is embedded within an instruction execution pipeline.

11. The apparatus of claim 10, wherein the instruction identification circuitry is embedded within a stage of the instruction execution pipeline that performs instruction decoding.

12. The apparatus of claim 9, wherein the first circuitry is embedded within a memory execution unit of an instruction execution pipeline.

13. The apparatus of claim 9, wherein the second circuitry is embedded within a memory execution unit of an instruction execution pipeline.

14. The apparatus of claim 9, further comprising first register space that stores first information indicating if bus lock assistance has been enabled for the first instruction and the second instruction, and bus lock assistance circuitry to read the first information.

15. The apparatus of claim 14, further comprising second register space that stores second information to indicate whether the first instruction is a bus lock instruction and the second instruction is a bus lock instruction, the instruction identification circuitry to write to the second register space.

16. The apparatus of claim 9, further comprising third circuitry to:

detect that bus lock assistance has been enabled for the first instruction as a pre-condition to preventing the initial bus lock from being imposed for the first instruction, and

detect that bus lock assistance has been enabled for the second instruction as a pre-condition to permitting the initial bus lock to be imposed for the second instruction.

17. The apparatus of claim 9, wherein the bus lock assistance function further is to prevent a bus lock protocol from being followed.

18. The apparatus of claim 9, wherein the bus lock assistance function further is to raise a second flag to indicate the initial bus lock is permitted for the second instruction.

19. A non-transitory machine readable medium containing program instructions that when processed by a processing core causes a method to be performed, the method comprising:

detecting that a first instruction and a second instruction are locked instructions;

determining that execution of the first instruction and the second instruction includes imposing an initial bus lock; and

executing a bus lock assistance function in response to the determining, wherein the bus lock assistance function comprises;

preventing the initial bus lock from being imposed for the first instruction by raising a flag to cause execution of software including the first instruction to stop, and

permitting the initial bus lock to be imposed for the second instruction.

20. The non-transitory machine readable medium of claim 19, wherein the determining that the execution of the first instruction and the second instruction each includes imposing the initial bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not cacheable.

21. The non-transitory machine readable medium of claim 19, wherein the determining that the execution of the first instruction and the second instruction includes imposing the initial bus lock includes determining that a memory type of each of the first instruction and the second instruction does not permit a cache lock.

22. The non-transitory machine readable medium of claim 19, wherein the determining that the execution of the first instruction and the second instruction includes imposing the initial bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not within a cache.

23. The non-transitory machine readable medium of claim 19, wherein the determining that the execution of the first instruction and the second instruction includes imposing the initial bus lock includes determining that an address of a data item to be fetched by each of the first instruction and the second instruction crosses a cache line boundary.

24. The non-transitory machine readable medium of claim 19, wherein the bus lock assistance function further comprises raising a second flag to indicate the initial bus lock is permitted for the second instruction.

25. The non-transitory machine readable medium of claim 19, wherein the method further comprises detecting that bus lock assistance has been enabled for the first instruction as a pre-condition to preventing the initial bus lock from being imposed for the first instruction, and detecting that bus lock assistance has been enabled for the second instruction as a pre-condition to permitting the initial bus lock to be imposed for the second instruction.