Refreshing of dynamic random access memory
First Claim
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1. A dynamic random access memory controller, comprising:
- a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory; and
a microcontroller, using a counter to count how many times a rank of the dynamic random access memory is entirely refreshed,wherein;
the microcontroller repeatedly performs a per-rank refresh operation on the rank when the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue;
the microcontroller decreases the counter by 1 every refresh inspection interval;
when there are access commands corresponding to the rank waiting in the command queue and the counter is 0, the microcontroller refreshes the rank bank-by-bank by per-bank refresh operations;
corresponding to a per-bank refresh operation to be performed on a single bank within the rank, the microcontroller raises priority of access commands queued in the command queue corresponding to remaining banks of the rank except for the single bank; and
when finishing the per-bank refresh operation on the single bank, the microcontroller restores the priority of the access commands queued in the command queue corresponding to the remaining banks of the rank except for the single bank.
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Abstract
A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.
7 Citations
14 Claims
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1. A dynamic random access memory controller, comprising:
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a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory; and a microcontroller, using a counter to count how many times a rank of the dynamic random access memory is entirely refreshed, wherein; the microcontroller repeatedly performs a per-rank refresh operation on the rank when the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue; the microcontroller decreases the counter by 1 every refresh inspection interval; when there are access commands corresponding to the rank waiting in the command queue and the counter is 0, the microcontroller refreshes the rank bank-by-bank by per-bank refresh operations; corresponding to a per-bank refresh operation to be performed on a single bank within the rank, the microcontroller raises priority of access commands queued in the command queue corresponding to remaining banks of the rank except for the single bank; and when finishing the per-bank refresh operation on the single bank, the microcontroller restores the priority of the access commands queued in the command queue corresponding to the remaining banks of the rank except for the single bank. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A control method for dynamic random access memory, comprising:
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providing a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory; using a counter to count how many times a rank of the dynamic random access memory is entirely refreshed; repeatedly performing a per-rank refresh operation on the rank when the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue; decreasing the counter by 1 every refresh inspection interval; when there are access commands corresponding to the rank waiting in the command queue and the counter is 0, refreshing the rank bank-by-bank by per-bank refresh operations; corresponding to a per-bank refresh operation to be performed on a single bank within the rank, priority of access commands queued in the command queue corresponding to remaining banks of the rank except for the single bank is raised; and when finishing the per-bank refresh operation on the single bank, the priority of the access commands queued in the command queue corresponding to the remaining banks of the rank except for the single bank is restored. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification