Refreshing of dynamic random access memory

• US 10,216,658 B2
• Filed: 05/19/2017
• Issued: 02/26/2019
• Est. Priority Date: 02/16/2017
• Status: Active Grant

• Current Assignee: Via Alliance Semiconductor Co., Ltd.
• Original Assignee: Via Alliance Semiconductor Co., Ltd.
• Inventors: Chen, Chen, Shen, Peng
• Primary Examiner(s): Cygiel, Gary W.
• Application Number:
  US15/599,818
• Publication Number:
  US 20180232329A1
• Time in Patent Office: 648 Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H05K 2201/10159 Memory

Abstract

A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.

Claims

1. A dynamic random access memory controller, comprising:

a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory; and

a microcontroller, using a counter to count how many times a rank of the dynamic random access memory is entirely refreshed,

wherein;

the microcontroller repeatedly performs a per-rank refresh operation on the rank when the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue;

the microcontroller decreases the counter by 1 every refresh inspection interval;

when there are access commands corresponding to the rank waiting in the command queue and the counter is 0, the microcontroller refreshes the rank bank-by-bank by per-bank refresh operations;

corresponding to a per-bank refresh operation to be performed on a single bank within the rank, the microcontroller raises priority of access commands queued in the command queue corresponding to remaining banks of the rank except for the single bank; and

when finishing the per-bank refresh operation on the single bank, the microcontroller restores the priority of the access commands queued in the command queue corresponding to the remaining banks of the rank except for the single bank.

2. The dynamic random access memory controller as claimed in claim 1, wherein:

the microcontroller stops repeating the per-rank refresh operation on the rank when the counter reaches the upper limit.

3. The dynamic random access memory controller as claimed in claim 1, wherein:

when there are access commands corresponding to the rank waiting in the command queue and the counter is greater than 0, the microcontroller gives the access commands corresponding to the rank a higher priority than refresh operations on the rank.

4. The dynamic random access memory controller as claimed in claim 1, wherein:

when performing the per-bank refresh operation on the single bank, the microcontroller further decreases priority of access commands queued in the command queue corresponding to the single bank.

5. The dynamic random access memory controller as claimed in claim 4, wherein:

when finishing the per-bank refresh operation on the single bank, the microcontroller restores the priority of the access commands queued in the command queue corresponding to the single bank.

6. The dynamic random access memory controller as claimed in claim 1, wherein:

when performing the per-rank refresh operation on the rank, the microcontroller further decreases priority of access commands queued in the command queue corresponding to the rank.

7. The dynamic random access memory controller as claimed in claim 6, wherein:

when finishing the per-rank refresh operation, the microcontroller restores the priority of the access commands queued in the command queue corresponding to the rank.

8. A control method for dynamic random access memory, comprising:

providing a command queue with access commands queued therein, wherein the access commands are queued in the command queue waiting to be transmitted to a dynamic random access memory;

using a counter to count how many times a rank of the dynamic random access memory is entirely refreshed;

repeatedly performing a per-rank refresh operation on the rank when the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue;

decreasing the counter by 1 every refresh inspection interval;

when there are access commands corresponding to the rank waiting in the command queue and the counter is 0, refreshing the rank bank-by-bank by per-bank refresh operations;

corresponding to a per-bank refresh operation to be performed on a single bank within the rank, priority of access commands queued in the command queue corresponding to remaining banks of the rank except for the single bank is raised; and

when finishing the per-bank refresh operation on the single bank, the priority of the access commands queued in the command queue corresponding to the remaining banks of the rank except for the single bank is restored.

9. The control method for dynamic random access memory as claimed in claim 8, further comprising:

stopping repeating the per-rank refresh operation on the rank when the counter reaches the upper limit.

10. The control method for dynamic random access memory as claimed in claim 8, wherein:

when there are access commands corresponding to the rank waiting in the command queue and the counter is greater than 0, the access commands corresponding to the rank are given a higher priority than refresh operations on the rank.

11. The control method for dynamic random access memory as claimed in claim 8, wherein:

when the per-bank refresh operation is performed on the single bank, priority of access commands queued in the command queue corresponding to the single bank is decreased.

12. The control method for dynamic random access memory as claimed in claim 11, wherein:

when the per-bank refresh operation on the single bank finishes, the priority of the access commands queued in the command queue corresponding to the single bank is restored.

13. The control method for dynamic random access memory as claimed in claim 8, wherein:

when the per-rank refresh operation is performed on the rank, priority of access commands queued in the command queue corresponding to the rank is decreased.

14. The control method for dynamic random access memory as claimed in claim 13, wherein:

when the per-rank refresh operation finishes, the priority of the access commands queued in the command queue corresponding to the rank is restored.