Memory modules with nonvolatile storage and rapid, sustained transfer rates

• US 10,216,685 B1
• Filed: 12/07/2017
• Issued: 02/26/2019
• Est. Priority Date: 07/19/2017
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Inventors: Sartore, Ronald H, Koger, Thomas O.
• Primary Examiner(s): Rojas, Midys
• Assistant Examiner(s): Doan, Khoa D
• Application Number:
  US15/834,490
• Time in Patent Office: 446 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A memory module is organized into slice sections, each configured to input and output a slice of data for a different section of a data bus. Each slice section includes at least one nonvolatile memory (NVM) and a memory element, such as random access volatile memory, to store the slice of data for the slice section during operations that transfer the slice of data between the section of the data bus for the slice section and the NVM of the slice section. Each slice section also includes a slice controller configured to translate an address for the slice of data for the section of the data bus into a physical address of the NVM of the slice section.

Claims

1. A memory module, comprising:

a data bus;

a plurality of slice sections, each slice section configured to input and output a slice of a data for a different section of the data bus;

each slice section comprising;

at least one nonvolatile memory (NVM);

a memory element to store the slice of the data for the slice section during operations that transfer the slice of the data between the section of the data bus for the slice section and the NVM of the slice section; and

a slice controller configured to translate an address for the slice of the data for the section of the data bus into at least a physical address of the NVM of the slice section; and

the memory element comprising a multi-port random access memory having at least a first address port coupled to receive address data from an address bus common to the plurality of slice sections and at least a second address port coupled to receive an address from the slice controller of the slice section;

wherein the slice controller is configured to simultaneously;

transfer data between the corresponding NVM and the corresponding memory element of the slice section, and transfer data between the corresponding memory element of the slice section and the address bus.

2. The memory module of claim 1, the memory element comprising a multi-port random access memory having at least a first data port coupled to the section of the data bus for the slice section, and at least a second data port coupled to the NVM of the slice section.

3. The memory module of claim 1, the memory element configured to cache at least a portion of data stored in the NVM of the slice section.

4. The memory module of claim 1, the memory element comprising a physical slave interface responsive to a master device to transfer the slice of data over the section of the data bus for the slice section.

5. The memory module of claim 1, the slice controller comprising:

at least one processor; and

at least one processor memory configured to store instructions executable by the at least one processor for operating the NVM of the slice section.

6. The memory module of claim 1, further comprising:

the data bus is part of a memory bus;

the memory module further comprising;

a master controller configured to generate at least slice address values in response to address and control signals received on the memory bus; and

a slice address bus, that couples to the master controller, to transfers the slice address value to each slice section.

7. A system, comprising:

a plurality of memory modules coupled to a system memory bus interface, each memory module including nonvolatile memory (NVM) arranged into slice sections that each store a slice of a data for different portions of an access transfer width of a system memory bus;

a module bus; and

a slice controller corresponding to each slice section, each slice controller configured to access the slice of the data in the NVM of the corresponding slice section in response to address data received on the module bus;

the slice controller configured to translate an address for the slice of the data for the section of the data bus into at least a physical address of the NVM of the slice section; and

wherein each of the memory modules further comprising;

a data slice store, the data slice store to cache a portion of data stored in the NVM of the corresponding slice section; and

wherein the data slice store comprising a multi-port random access memory having at least a first address port coupled to receive address data from an address bus common to the plurality of slice sections and at least a second address port coupled to receive an address from the slice controller of the slice section;

wherein the slice controller is configured to simultaneously;

transfer data between the corresponding NVM and the corresponding data slice store of the slice section, and transfer data between the corresponding data slice store of the slice section and the system memory bus.

8. The system of claim 7, further comprising:

a master controller coupled between the module bus and the address and control portion of the system memory bus and configured to generate the address data on the module bus.

9. The system of claim 7, each of the memory modules further comprising:

a master controller configured to map predetermined bus address values received on the system memory bus to addresses in the data slice store.

10. The system of claim 7, each of the memory modules further comprising:

a slice communication channel to receive data from the slice controller.

11. The system of claim 10, each of the memory modules configured to generate at least one signal indicating a status of an access to the NVM based on signals received on the slice communication channel.

12. The system of claim 10, each of the memory modules configured to generate at least one signal indicating a status of accesses to the NVMs of each corresponding slice section based on signals received on the slice communication channel.

13. The system of claim 7, further comprising:

a slave memory bus interface circuit corresponding to each slice section; and

each slave memory bus interface circuit in communication with a master memory controller over a data portion of the system memory bus.

14. A method, comprising:

receiving different portions of a multi-bit data value from a memory bus at different slice sections of a memory module;

receiving an address value at a slice controller of each slice section, the address value corresponding to the multi-bit data value; and

storing the portions of the multi-bit data value each in a different slice section of a nonvolatile memory (NVM) according to the address value;

wherein storing the portions of the multi-bit data value includes caching each portion of the multi-bit value data in a data slice store of the corresponding slice section, and writing the portion of the multi-bit data value into the NVM corresponding to the slice section; and

wherein storing the portions of the multi-bit data value includes, for each slice section, translating the address value into an NVM address based on an address translation table unique to the slice section;

wherein the data slice store comprising a multi-port random access memory having at least a first address port coupled to receive address data from an address bus common to the plurality of slice sections and at least a second address port coupled to receive an address from a slice controller of the corresponding slice section;

wherein the slice controller is configured to simultaneously;

transfer data between the corresponding NVM and the corresponding data slice store of the slice section, and transfer data between the corresponding data slice store of the slice section and the system memory bus.

15. The method of claim 14, wherein storing the portions of the multi-bit data value includes, for each slice section, translating the address value into an NVM address based on an address translation table unique to the slice section.

16. The method of claim 14, further comprising:

within each slice section, in response to predetermined address values, outputting at least some of the cached data as a portion of the multi-bit data value corresponding to the predetermined address.

17. The method of claim 14, further comprising:

simultaneously;

transferring data between a data slice store of the slice section and the memory bus; and

accessing the NVM of the slice section with the slice controller of the slice section.