IC layout pattern matching and classification system and method
First Claim
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1. A method for classifying patterns in a set of layout patterns, comprising:
- decomposing each of a plurality of pattern windows of an integrated circuit layout into a low frequency and a high frequency component using a wavelet analysis;
computing a plurality of moments for each of the plurality of pattern windows of the integrated circuit layout using the low frequency component as an approximation;
classifying the plurality of pattern windows into pattern classes using a distance computation for respective moments of the plurality of pattern windows by comparing the distance computation to an error value to determine similarities between the plurality of pattern windows, the classifying including generating a preferred set of integrated circuit layout designs for a particular technology node; and
fabricating one or more integrated circuit chips using one or more of the generated preferred set of integrated circuit layout designs.
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Abstract
A system and method for restricting the number of layout patterns by pattern identification, matching and classification, includes decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis for an integrated circuit layout having a plurality of pattern windows. Using the low frequency component as an approximation, a plurality of moments is computed for each pattern window. The pattern windows are classified using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.
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18 Claims
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1. A method for classifying patterns in a set of layout patterns, comprising:
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decomposing each of a plurality of pattern windows of an integrated circuit layout into a low frequency and a high frequency component using a wavelet analysis; computing a plurality of moments for each of the plurality of pattern windows of the integrated circuit layout using the low frequency component as an approximation; classifying the plurality of pattern windows into pattern classes using a distance computation for respective moments of the plurality of pattern windows by comparing the distance computation to an error value to determine similarities between the plurality of pattern windows, the classifying including generating a preferred set of integrated circuit layout designs for a particular technology node; and fabricating one or more integrated circuit chips using one or more of the generated preferred set of integrated circuit layout designs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for classifying patterns in a set of layout patterns, comprising:
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computing a plurality of moments for each of a plurality of pattern windows of an integrated circuit layout using a low frequency component of a wavelet analysis as an approximation; classifying the plurality of pattern windows into pattern classes using a distance computation for respective moments of the plurality of pattern windows by comparing the distance computation to an error value to determine similarities between the plurality of pattern windows, the classifying including generating a preferred set of integrated circuit layout designs for a particular technology node; and fabricating one or more integrated circuit chips using one or more of the generated preferred set of integrated circuit layout designs. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification