Integrated circuits having in-situ constraints

• US 10,216,890 B2
• Filed: 02/23/2018
• Issued: 02/26/2019
• Est. Priority Date: 04/21/2004
• Status: Expired due to Fees

• Current Assignee: IYM Technologies LLC (General Patent Corporation)
• Original Assignee: IYM Technologies LLC (General Patent Corporation)
• Inventors: Qian, Qi-De
• Primary Examiner(s): Levin, Naum
• Application Number:
  US15/903,674
• Publication Number:
  US 20180181699A1
• Time in Patent Office: 368 Days
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.

Claims

1. A method of increasing manufacturability of a design layout of an integrated circuit product fabricated using a manufacturing process performed by an integrated circuit fabrication system, comprising:

defining an original design layout based on original design rules associated with the manufacturing process, the original design rules comprising at least global limits on relative distance between layout objects, and a design layout process comprising at least one optimization process on features of the original design layout;

generating a modified design layout by an automated design layout system, based at least on the original design layout, the original design rules, and a set of location-specific limits on relative distance between layout objects of the original design layout which are looked up from a predetermined table using patterns of layout objects in the original design layout defined by the design layout process, as look-up keys; and

outputting the modified design layout in a format suitable for use by the integrated circuit fabrication system to fabricate the integrated circuit product.

2. The method according to claim 1, wherein the at least one optimization process optimizes according to an objective function.

3. The method according to claim 1, further comprising manufacturing the integrated circuit product by the integrated circuit fabrication system based on the modified design layout.

4. The method according to claim 3, wherein the original design layout has a process latitude, with respect to the integrated circuit fabrication system, and the modified design layout has an improved process latitude over the original design layout.

5. The method according to claim 1, wherein the set of location-specific limits on relative distance between layout objects of the original design layout are anisotropic.

6. The method according to claim 1, wherein the original design layout comprises a first plurality of routing wires running in a first direction, and a second plurality of routing wires running in a second direction, the second direction being orthogonal to the first direction, the routing wires of the first plurality of routing wires having first width values, the routing wires of the second plurality of routing wires having second width values, the first width values being substantially different from the second width values.

7. The method according to claim 6, wherein the step of generating a modified design layout comprises locally adjusting at least a width value of at least one of the first plurality of routing wires.

8. The method according to claim 6, wherein the step of generating a modified design layout comprises locally adjusting at least a spacing value between a pair of the first plurality of routing wires.

9. The method according to claim 1, wherein the original design layout comprises interrelated layout objects organized in a hierarchical structure including master instances, cell instances, and array instances.

10. The method according to claim 1, wherein the patterns of layout objects within the original design layout comprises interrelated layout objects on one layer of the original design layout.

11. The method according to claim 10, wherein the patterns of layout objects within the design layout comprises a combination of geometry of adjacent layout objects within the original design layout.

12. The method according to claim 1, wherein the patterns of layout objects are determined by performing automated pattern recognition.

13. The method according to claim 12, wherein the automated pattern recognition comprises recognizing combinations of geometry in the original design layout.

14. The method according to claim 1, wherein:

the original design rules comprise a minimum safeguard distance limit; and

the step of generating a modified design layout by an automated design layout system comprises generating an additional safeguard distance, and adding the additional safeguard distance to the minimum safeguard distance limit.

15. The method according to claim 1, wherein the original design rules are adapted for a particular manufacturing process, wherein occurrences of the patterns within the original design layout represent regions having a first local process latitude for the particular manufacturing process, and at least some of corresponding regions of the modified latitude represent regions of having a second local process latitude for the particular manufacturing process, wherein the second local process latitude is improved over the first local process latitude.

16. The method according to claim 1, further comprising further modifying the modified design layout selectively in at least one location of the modified design layout which limits a process latitude with respect to a photolithography process, dependent on a circuit tolerance at the at least one location.

17. The method according to claim 1, wherein said step of generating the modified design layout comprises modifying the original design layout by optimization according to an optimization objective in a presence of constraints imposed by at least the pattern-specific design rules.

18. The method according to claim 1, wherein said step of generating the modified design layout causes at least one new violation of the original design rules comprising at least global limits on relative distance between layout objects, further comprising optimizing the modified design layout according to at least one optimization objective.

19. The method according to claim 18, wherein the at least one optimization objective comprises wire length minimization, legalization, and compaction of the modified design layout.

20. A method of producing a mask design layout for an integrated circuit product for fabrication by an integrated circuit fabrication system according to a manufacturing process, comprising:

storing in a memory, a description of an original mask design layout based on original mask design rules associated with the manufacturing process, the original mask design rules comprising at least;

global limits on relative distance between layout objects within the mask design layout, and

a mask design layout process comprising at least one optimization process on features of the original mask design layout;

looking up a set of location-specific limits on relative distance between layout objects of the original mask design layout from a predetermined table, using patterns of layout objects in the original mask design layout defined by the mask design layout process, as look-up keys;

generating, by an automated mask design layout system, a modified mask design layout from the original mask design layout, wherein the set of location-specific limits on relative distance between layout objects of the original mask design layout regionally modify the original mask design rules; and

outputting the modified mask design layout in a format suitable for use by the integrated circuit fabrication system to fabricate the integrated circuit product.

21. The method according to claim 20, wherein said generating comprises employing at least one optimization process which optimizes modified regions of the mask design layout according to an objective function.

22. The method according to claim 21, further comprising manufacturing a modified mask design according to the modified mask design layout.

23. The method according to claim 22, further comprising employing the modified mask design in an integrated circuit manufacturing process having a predetermined process latitude dependent on a relative distance between layout objects represented in the modified mask design and respective features of adjacent respective layout objects to manufacture an integrated circuit, wherein the modified mask design regionally increases the relative distance with respect to the original mask design between layout objects represented in the modified mask design layout, selectively dependent on the respective features in a respective region of the original mask design layout, when an automated processor predicts, based on the predetermined table, an insufficient process latitude to reliably manufacture the integrated circuit.

24. The method according to claim 20, further comprising manufacturing the integrated circuit product by the circuit fabrication system based on the modified design layout.

25. The method according to claim 20, wherein the original design layout has a process latitude at a specific location, with respect to the integrated circuit fabrication system, and the modified design layout has an improved process latitude over the original design layout at the specific location.