Multi-layer stack with embedded tamper-detect protection

• US 10,217,336 B2
• Filed: 07/30/2018
• Issued: 02/26/2019
• Est. Priority Date: 02/25/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busby, James A., Isaacs, Phillip Duane, Santiago-Fernandez, William
• Primary Examiner(s): Hunnings, Travis R
• Application Number:
  US16/048,650
• Publication Number:
  US 20180365947A1
• Time in Patent Office: 211 Days
• CPC Class Codes: G08B 13/12 by the breaking or disturbance of stretched cords or wires
• CPC Class Codes: G08B 13/128 the housing being an electronic circuit unit, e.g. memory or CPU chip protecting computer components in secure or tamper resistant housings G06F21/86; protecting computer input devices, e.g. keyboards G06F21/83

Abstract

Tamper-respondent assemblies and methods of fabrication are provided which include a multi-layer stack having multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers. Further, the tamper-respondent assembly includes a tamper-respondent electronic circuit structure embedded within the multi-layer stack. The tamper-respondent electronic circuit structure includes at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack. The tamper-respondent electronic circuit structure defines a secure volume within the multi-layer stack. For instance, the tamper-respondent electronic circuit structure may be fully embedded within the multi-layer stack, with monitor circuitry of the tamper-respondent electronic circuit structure residing within the secure volume within the multi-layer stack.

Claims

1. A tamper-respondent assembly comprising:

a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers;

a tamper-respondent electronic circuit structure embedded within the multi-layer stack, the tamper-respondent electronic circuit structure comprising at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack, the tamper-respondent electronic circuit structure defining a secure volume within the multi-layer stack;

wherein the multi-layer stack comprises a first component layer, at least one in-between component layer, and a second component layer stacked together, the at least one in-between component layer being disposed between the first component layer and the second component layer in the multi-layer stack, and wherein the tamper-respondent electronic circuit structure is associated with the first component layer, the at least one in-between component layer, and the second component layer, with the secure volume being defined, at least in part, within the at least one in-between component layer; and

wherein the multi-layer stack comprises multiple in-between component layers disposed between the first component layer and the second component layer, the at least one in-between component layer being at least one in-between component layer of the multiple in-between component layers, and the at least one tamper-respondent sensor comprises at least one peripheral tamper-detect circuit, the at least one peripheral tamper-detect circuit including respective pluralities of through-substrate vias, each plurality extending through a respective component layer of the multiple in-between component layers, at least some through-substrate vias of the respective pluralities of through-substrate vias being electrically interconnected in the at least one peripheral tamper-detect circuit by respective electrical contacts of the plurality of electrical contacts disposed in between component layers of the multi-layer stack.

2. The tamper-respondent assembly of claim 1, wherein the at least one tamper-respondent sensor comprises at least one lower tamper-detect circuit within the first component layer and at least one upper tamper-detect circuit within the second component layer.

3. The tamper-respondent assembly of claim 1, wherein the at least one tamper-respondent sensor embedded, at least in part, within the at least one component layer comprises multiple stacked tamper-detect circuits within one component layer of the at least one component layer of the multi-layer stack.

4. The tamper-respondent assembly of claim 1, wherein the tamper-respondent electronic circuit structure is embedded within the multi-layer stack, and the secure volume resides fully within the multi-layer stack.

5. A method of fabricating a tamper-respondent assembly comprising:

providing a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers;

embedding a tamper-respondent electronic circuit structure within the multi-layer stack, the tamper-respondent electronic circuit structure comprising at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack, the tamper-respondent electronic circuit structure defining a secure volume within the multi-layer stack;

wherein the multi-layer stack comprises a first component layer, at least one in-between component layer, and a second component layer stacked together, the at least one in-between component layer being disposed between the first component layer and the second component layer in the multi-layer stack, and wherein embedding the tamper-respondent electronic circuit structure within the multi-layer stack comprises associating the tamper-respondent electronic circuit structure with the first component layer, the at least one in-between component layer, and the second component layer, with the secure volume being defined, at least in part, within the at least one in-between component layer; and

wherein the multi-layer stack comprises multiple in-between component layers disposed between the first component layer and the second component layer, the at least one in-between component layer being at least one in-between component layer of the multiple in-between component layers, and the at least one tamper-respondent sensor comprises at least one peripheral tamper-detect circuit, the at least one peripheral tamper-detect circuit including respective pluralities of through-substrate vias, each plurality extending through a respective component layer of the multiple in-between component layers, at least some through-substrate vias of the respective pluralities of through-substrate vias being electrically interconnected in the at least one peripheral tamper-detect circuit by respective electrical contacts of the plurality of electrical contacts disposed in between component layers of the multi-layer stack.

6. The method of claim 5, wherein the at least one tamper-respondent sensor comprises at least one lower tamper-detect circuit within the first component layer and at least one upper tamper-detect circuit within the second component layer.

7. The method of claim 5, further comprising an under-fill material disposed between adjacent component layers of the multiple discrete component layers, the under-fill material surrounding, at least in part, electrical contacts of the plurality of electrical contacts in between the component layers.

8. The method of claim 5, wherein the at least one tamper-respondent sensor embedded, at least in part, within the at least one component layer comprises multiple stacked tamper-detect circuits within one component layer of the at least one component layer of the multi-layer stack.

9. The method of claim 5, wherein the tamper-respondent electronic circuit structure is embedded within the multi-layer stack, and the secure volume resides fully within the multi-layer stack.

10. A method of fabricating a tamper-respondent assembly comprising:

providing a multi-layer stack comprising multiple discrete component layers stacked and electrically connected together via a plurality of electrical contacts in between the component layers;

embedding a tamper-respondent electronic circuit structure within the multi-layer stack, the tamper-respondent electronic circuit structure comprising at least one tamper-respondent sensor embedded, at least in part, within at least one component layer of the multiple discrete component layers of the multi-layer stack, the tamper-respondent electronic circuit structure defining a secure volume within the multi-layer stack;

wherein the multi-layer stack comprises a first component layer, at least one in-between component layer, and a second component layer stacked together, the at least one in-between component layer being disposed between the first component layer and the second component layer in the multi-layer stack, and wherein embedding the tamper-respondent electronic circuit structure within the multi-layer stack comprises associating the tamper-respondent electronic circuit structure with the first component layer, the at least one in-between component layer, and the second component layer, with the secure volume being defined, at least in part, within the at least one in-between component layer;

wherein the at least one tamper-respondent sensor comprises at least one lower tamper-detect circuit within the first component layer and at least one upper tamper-detect circuit within the second component layer;

wherein the at least one tamper-respondent sensor further comprises at least one peripheral tamper-detect circuit, the at least one peripheral tamper-detect circuit defined, at least in part, by a plurality of through-substrate vias extending through the at least one in-between component layer, wherein the at least one upper tamper-detect circuit, the at least one lower tamper-detect circuit, and the at least one peripheral tamper-detect circuit electrically connect to monitor circuitry of the tamper-respondent electronic circuit structure and facilitate defining the secure volume within the multi-layer stack; and

wherein the multi-layer structure resides on a base component layer, the base component layer being a 2.5D interposer.