Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch

• US 10,217,494 B2
• Filed: 06/28/2017
• Issued: 02/26/2019
• Est. Priority Date: 06/28/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Giridhar, Bharan, Cheema, Sachmanik, Hess, Greg M.
• Primary Examiner(s): Tran, Anthan
• Assistant Examiner(s): Siddique, Mushfique
• Application Number:
  US15/635,825
• Publication Number:
  US 20190005993A1
• Time in Patent Office: 608 Days
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.

Claims

1. A memory, comprising:

a plurality of banks, wherein each bank of the plurality of banks includes a plurality of data storage cells, wherein a particular bank of the plurality of banks is configured to discharge a particular global bit line of a plurality of global bit lines in response to a memory operation;

a control circuitry configured to;

receive information indicative of a control signal; and

select a first bank of the plurality of banks based upon the control signal; and

generate a plurality of bank enable signals using the control signal; and

a first latch circuit coupled to the first bank via a first global bit line of the plurality of global bit lines, and a second bank via a second global bit line of the plurality of global bit lines, wherein the first latch circuit is configured to;

store data based on a voltage level of the first global bit line;

pre-charge the first global bit line based upon the control signal;

generate a plurality of pre-charge signals using the plurality of bank enable signals; and

generate a reset signal based upon at least one pre-charge signal of the plurality of pre-charge signals, wherein the reset signal is delayed from the at least one pre-charge signal.

2. The memory of claim 1, wherein the memory further comprises a second latch circuit configured to store an output of the first latch circuit using a clock signal.

3. The memory of claim 1, wherein the first latch circuit is further configured to reset using the reset signal.

4. The memory of claim 1, wherein the memory further comprises one or more p-channel metal-oxide semiconductor field-effects transistors (MOSFETs) coupled to the particular global bit line, and wherein to pre-charge the particular global bit line, the memory is further configured to activate the one or more p-channel MOSFETs.

5. A method, comprising:

receiving, by a multi-bank memory, data indicative of an address location in the multi-bank memory;

decoding the data indicative of the address location to generate a decoded address;

generating a plurality of pre-charge signals using the decoded address;

initiating a read operation of a particular bank of a plurality of banks included in the multi-bank memory using the decoded address, wherein initiating the read operation includes;

pre-charging, using the plurality of pre-charge signals, a particular global bit line of a plurality of global bit lines coupled to the particular bank;

generating a reset signal using at least one pre-charge signal of the plurality of pre-charge signals, wherein the reset signal is delayed from the at least one pre-charge signal;

storing, in a first latch circuit, data based on a voltage level of the particular global bit line using the plurality of pre-charge signals; and

resetting the first latch circuit using the reset signal.

6. The method of claim 5, wherein generating the reset signal includes performing a logical-NOR operation using the at least one pre-charge signal and another pre-charge signal of the plurality of pre-charge signals.

7. The method of claim 5 further comprising, storing, by a second latch circuit, an output of the first latch circuit using a clock signal.

8. The method of claim 5, further comprising generating the plurality of pre-charge signals using at least a first bank enable signal and a second bank enable signal that are based upon the decoded address.

9. The method of claim 5, wherein pre-charging, using the plurality of pre-charge signals, the particular global bit line includes activating at least one p-channel metal-oxide semiconductor field-effect transistor coupled to the particular global bit line.

10. A system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory includes a plurality of banks, wherein each bank of the plurality of banks includes a plurality of data storage cells, and wherein the memory is configured to;

receive an access operation from the processor;

decode an address included in the access operation to generated a decoded address;

select a particular bank of the plurality of banks using the decoded address;

generate a plurality of pre-charge signals using a plurality of bank enable signals that are based upon the decoded address;

store a data value based upon a voltage level of a global bit line coupled to the particular bank using the plurality of pre-charge signals; and

pre-charge the global bit line using a particular pre-charge signal of the plurality of pre-charge signals.

11. The system of claim 10, wherein the memory includes a plurality of latch circuits, and wherein the memory is further configured to store the data value based upon the voltage level of the global bit line using a particular latch circuit of the plurality of latch circuits.

12. The system of claim 11, wherein the memory is further configured to generate a reset signal using at least one pre-charge signal of the plurality of pre-charge signals, wherein the reset signal is delayed from the at least one pre-charge signal.

13. The system of claim 12, wherein the memory is further configured to reset the particular latch circuit using the reset signal.

14. The system of claim 11, wherein the memory is further configured to store an output of the particular latch circuit using another latch circuit of the plurality of latch circuits based on a clock signal.

15. The system of claim 10, wherein to pre-charge the global bit line, the memory is further configured to activate at least one p-channel metal-oxide semiconductor field-effect transistor coupled to the global bit line.