Tunable negative bitline write assist and boost attenuation circuit

• US 10,217,510 B2
• Filed: 10/31/2017
• Issued: 02/26/2019
• Est. Priority Date: 01/12/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chandra, Dinesh, Potladhurthi, Eswararao, Reddy, Dhani Reddy Sreenivasula, Rengarajan, Krishnan S.
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Bermudez Lozada, Alfredo
• Application Number:
  US15/798,764
• Publication Number:
  US 20180068717A1
• Time in Patent Office: 483 Days
• Field of Search: 365156
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.

Claims

1. An SRAM write assist attenuation device, comprising:

a write driver connected to bit lines in each of a plurality of SRAM cells of the memory array; and

a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising;

a clamping device comprising a first NFET, a second NFET, and a third NFET connected to a common control signal; and

a logic structure configured to generate a first attenuation signal, a second attenuation signal, and a third attenuation signal,

wherein the logic structure is coupled to the first NFET, the second NFET, and the third NFET to provide the first attenuation signal, the second attenuation signal, and the third attenuation signal to the first NFET, the second NFET, and the third NFET, respectively, to attenuate an amount of boost applied to pull one of the bit lines below ground in response to at least one of the first attenuation signal, the second attenuation signal, and the third attenuation signal,

wherein a width of a channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the common control signal in a different manner, and

wherein the channel width of the first NFET is configured to provide a default attenuation to the amount of boost, the channel width of the second NFET is configured to provide an attenuation less than the default attenuation to the amount of boost, and the channel width of the third NFET is configured to provide an attenuation greater than the default attenuation to the amount of boost.

2. The SRAM write assist attenuation device of claim 1, wherein a source of the first NFET is connected to the common control signal, a drain of the first NFET is connected to a voltage control signal, and a gate of the first NFET is connected to the first attenuation signal.

3. The SRAM write assist attenuation device of claim 2, wherein a source of the second NFET is connected to the common control signal, a drain of the second NFET is connected to the voltage control signal, and a gate of the second NFET is connected to the second attenuation signal.

4. The SRAM write assist attenuation device of claim 3, wherein a source of the third NFET is connected to the common control signal, a drain of the third NFET is connected to the voltage control signal, and a gate of the third NFET is connected to the third attenuation signal.

5. The SRAM write assist attenuation device of claim 1, wherein the logic structure comprises an OR gate configured to generate a pulsed signal on the first attenuation signal, the second attenuation signal, and the third attenuation signal to allow for clamping of a n-channel metaloxidesemiconductor field-effect transistor disable (NDIS) signal until and during the boost and allow for the NDIS signal to proceed to the ground after the boost.

6. The SRAM write assist attenuation device of claim 1, wherein the first, second and third attenuation signals are different from one another.

7. The SRAM write assist attenuation device of claim 6, wherein source-drain paths of the first NFET, the second NFET and the third NFET are connected in parallel to one another and are each connected to the common control signal.