Nonvolatile memory devices, operating methods thereof and memory systems including the same

• US 10,217,516 B2
• Filed: 06/07/2016
• Issued: 02/26/2019
• Est. Priority Date: 02/09/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Han, Jinman, Chae, Donghyuk
• Primary Examiner(s): King, Douglas
• Application Number:
  US15/175,173
• Publication Number:
  US 20160284416A1
• Time in Patent Office: 994 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

Claims

1. An operating method of a nonvolatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of cell strings including memory cells stacked a direction perpendicular to a substrate and being connected to a plurality of string selection lines and a plurality of word lines, each cell string comprising a string selection transistor connected to a string selection line and a plurality of memory cells connected to the plurality of word lines respectively, the method comprising:

erasing first memory cells of first cell strings connected to at least one first string selection line in a selected memory block; and

during the erasing the first memory cells, preventing an erasure of second memory cells of second cell strings connected to at least one second string selection line in the selected memory block,

wherein, in the plurality of cell strings of each memory block, memory cells having a same order from string selection transistors are connected to a common word line among the plurality of word lines,

wherein each cell string further comprises a ground selection transistor connected to a ground selection line, and

wherein erasing the first memory cells comprises,

applying an erase voltage to the substrate,

applying word line erase voltages to the plurality of word lines, and

floating the at least one first string selection line and at least one first ground selection line connected to the first cell strings.

2. The operating method of claim 1, wherein preventing the erasure of the second memory cells comprises:

applying an erasure prohibition voltage to the at least one second string selection line and at least one second ground selection line connected to the second cell strings.

3. The operating method of claim 2, wherein the erase prohibition voltage controls ground selection transistors of the second cell strings such that the erase voltage is not supplied to the second memory cells.

4. The operating method of claim 1, further comprising:

receiving a first erase command and a first address identifying the first cell strings,

wherein the erasing the first memory cells and the preventing the erasure of the second memory cells are performed in response to the first erase command and the first address.

5. The operating method of claim 4, further comprising:

receiving a second erase command and a second address identifying the second cell strings; and

erasing the second memory cells and preventing an erasure of the first memory cells in response to the second erase command and the second address.

6. An operating method of a nonvolatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of cell strings including memory cells stacked a direction perpendicular to a substrate and being connected to a plurality of string selection lines and a plurality of word lines, each cell string comprising a selection transistor connected to a selection line and a plurality of memory cells connected to the plurality of word lines respectively, the method comprising:

applying a erase voltage to the substrate;

floating at least one first selection line connected to first cell strings in a selected memory block;

applying a erase prohibition voltage to at least one second selection line in the selected memory block during the applying the erase voltage to the substrate; and

applying word line erase voltages to the plurality of word lines in the selected memory block,

wherein, in the plurality of cell strings of each memory block, memory cells having a same order from selection transistors are connected to a common word line among the plurality of word lines.

7. The operating method of claim 6, wherein the selection transistor of each cell string comprises a string selection transistor connected to a string selection line and a ground selection transistor connected to a ground selection line.

8. The operating method of claim 6, wherein memory cells of the first cell strings are erased simultaneously.

9. The operating method of claim 6, wherein memory cells of the second cell strings are not erased.

10. The operating method of claim 6, further comprising:

receiving an erase command and an address identifying the first cell strings,

wherein applying the erase voltage, floating the at least one first selection line, applying the erase prohibition voltage, and applying the word line erase voltage are performed in response to the erase command and the address.