Nonvolatile memory devices, operating methods thereof and memory systems including the same
First Claim
1. An operating method of a nonvolatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of cell strings including memory cells stacked a direction perpendicular to a substrate and being connected to a plurality of string selection lines and a plurality of word lines, each cell string comprising a string selection transistor connected to a string selection line and a plurality of memory cells connected to the plurality of word lines respectively, the method comprising:
- erasing first memory cells of first cell strings connected to at least one first string selection line in a selected memory block; and
during the erasing the first memory cells, preventing an erasure of second memory cells of second cell strings connected to at least one second string selection line in the selected memory block,wherein, in the plurality of cell strings of each memory block, memory cells having a same order from string selection transistors are connected to a common word line among the plurality of word lines,wherein each cell string further comprises a ground selection transistor connected to a ground selection line, andwherein erasing the first memory cells comprises,applying an erase voltage to the substrate,applying word line erase voltages to the plurality of word lines, andfloating the at least one first string selection line and at least one first ground selection line connected to the first cell strings.
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Abstract
Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.
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Citations
10 Claims
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1. An operating method of a nonvolatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of cell strings including memory cells stacked a direction perpendicular to a substrate and being connected to a plurality of string selection lines and a plurality of word lines, each cell string comprising a string selection transistor connected to a string selection line and a plurality of memory cells connected to the plurality of word lines respectively, the method comprising:
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erasing first memory cells of first cell strings connected to at least one first string selection line in a selected memory block; and during the erasing the first memory cells, preventing an erasure of second memory cells of second cell strings connected to at least one second string selection line in the selected memory block, wherein, in the plurality of cell strings of each memory block, memory cells having a same order from string selection transistors are connected to a common word line among the plurality of word lines, wherein each cell string further comprises a ground selection transistor connected to a ground selection line, and wherein erasing the first memory cells comprises, applying an erase voltage to the substrate, applying word line erase voltages to the plurality of word lines, and floating the at least one first string selection line and at least one first ground selection line connected to the first cell strings. - View Dependent Claims (2, 3, 4, 5)
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6. An operating method of a nonvolatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of cell strings including memory cells stacked a direction perpendicular to a substrate and being connected to a plurality of string selection lines and a plurality of word lines, each cell string comprising a selection transistor connected to a selection line and a plurality of memory cells connected to the plurality of word lines respectively, the method comprising:
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applying a erase voltage to the substrate; floating at least one first selection line connected to first cell strings in a selected memory block; applying a erase prohibition voltage to at least one second selection line in the selected memory block during the applying the erase voltage to the substrate; and applying word line erase voltages to the plurality of word lines in the selected memory block, wherein, in the plurality of cell strings of each memory block, memory cells having a same order from selection transistors are connected to a common word line among the plurality of word lines. - View Dependent Claims (7, 8, 9, 10)
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Specification