3D semiconductor device, fabrication method and system

• US 10,217,667 B2
• Filed: 02/24/2018
• Issued: 02/26/2019
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Wurman, Zeev
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US15/904,347
• Publication Number:
  US 20180218946A1
• Time in Patent Office: 367 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/05687 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05688
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80006 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/17704 : the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17756 : for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 : for reliability
• CPC Class Codes: H03K 19/17796 : for physical disposition of blocks
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A 3D memory device, the device including: a first single crystal layer including memory peripheral circuits; a first memory layer including a first junction-less transistor; a second memory layer including a second junction-less transistor; and a third memory layer including a third junction-less transistor, where the first memory layer overlays the first single crystal layer, where the second memory layer overlays the first memory layer, where the third memory layer overlays the second memory layer, where the first junction-less transistor, the second junction-less transistor and the third junction-less transistor are formed by a single lithography and etch process, and where the first memory layer includes a nonvolatile NAND type memory.

Claims

1. A method for fabrication of a 3D semiconductor device, the method comprising:

providing a substrate comprising a single crystal layer;

forming a plurality of first transistors in and on said single crystal layer;

then

forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,

wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits, said peripheral circuits comprise decoder circuits;

then

forming a stack of at least sixteen layers,

wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,

wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,

wherein said first material is of a different composition than said second material, and

wherein said forming said stack is performed as part of forming a multilevel memory structure; and

then

processing said stack of at least sixteen layers forming at least eight layers of memory cells,

wherein said at least eight layers of memory cells are controlled by said periphery circuits,

wherein at least said forming said stack of at least sixteen layers and said processing said stack of at least sixteen layers comprise forming a staircase structure,

wherein said staircase structure comprises a portion of connection paths from said peripheral circuits to at least one of said memory cells,

wherein at least one of said memory cells overlays said peripheral circuits,

wherein each of said memory cells comprises at least one second transistor, said second transistor comprises a source, channel, and drain, and

wherein said source, said channel, and said drain comprise similar doping.

2. The method according to claim 1,

wherein said processing said stack of at least sixteen layers comprises annealing of said first transistors.

3. The method according to claim 1,

wherein said processing said stack of at least sixteen layers comprises forming metal layers as part of forming connections between said peripheral circuits and said memory cells.

4. The method according to claim 1,

wherein said memory cells are part of a non-volatile NAND memory.

5. The method according to claim 1,

wherein said memory cells are arranged as memory arrays, and

wherein transport of control signals to said memory cells and said memory arrays comprise a plurality of word-lines and a plurality of bit-lines.

6. The method according to claim 1,

wherein said processing said stack of at least sixteen layers comprises Atomic Layer Deposition (ALD).

7. The method according to claim 1, further comprising:

a first set of external connections underlying said single crystal layer to connect said device to a first external device; and

a second set of external connections overlying said at least eight layers of memory cells to connect said device to a second external device,

wherein said first set of external connections comprises a through silicon via (TSV).

8. A method for fabrication of a 3D semiconductor device, the method comprising:

providing a substrate comprising a single crystal layer;

forming a plurality of first transistors in and on said single crystal layer;

then

forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,

wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits, said peripheral circuits comprise decoder circuits;

then

forming a stack of at least sixteen layers,

wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,

wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,

wherein said first material is of a different composition than said second material, and

wherein said forming said stack is performed as part of forming a multilevel memory structure; and

then

processing said stack of at least sixteen layers forming at least eight layers of memory cells,

wherein said at least eight layers of memory cells are controlled by said periphery circuits,

wherein at least said forming said stack of at least sixteen layers and said processing said stack of at least sixteen layers comprise forming a staircase structure,

wherein said staircase structure comprises a portion of connection paths from said peripheral circuits to at least one of said memory cells,

wherein at least one of said memory cells overlays said peripheral circuits.

9. The method according to claim 8,

wherein said processing said stack of at least sixteen layers comprises annealing of said first transistors.

10. The method according to claim 8,

wherein each of said memory cells comprises at least one second transistor, said second transistor comprises a source, channel, and drain, and

wherein said source, said channel, and said drain comprise similar doping.

11. The method according to claim 8,

wherein said processing said stack of at least sixteen layers comprises forming metal layers as part of forming connections between said periphery circuits and said memory cells.

12. The method according to claim 8,

wherein said memory cells are part of a non-volatile NAND memory.

13. The method according to claim 8,

wherein said processing said stack of at least sixteen layers comprises use of Atomic Layer Deposition (ALD).

14. The method according to claim 8, further comprising:

forming a first set of external connections underlying said single crystal layer to connect said device to a first external device; and

forming a second set of external connections overlying said at least eight layers of memory cells to connect said device to a second external device,

wherein said first set of external connections comprises a through silicon via (TSV).

15. A method for fabrication of a 3D semiconductor device, the method comprising:

providing a substrate comprising a single crystal layer;

forming a plurality of first transistors in and on said single crystal layer;

then

forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,

wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits;

then

forming a stack of at least sixteen layers,

wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,

wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,

wherein said first material is of a different composition than said second material, and

wherein said forming said stack is performed as part of forming a multilevel memory structure; and

then

processing said stack of at least sixteen layers forming at least eight layers of memory cells,

wherein said at least eight layers of memory cells are controlled by said periphery circuits.

16. The method according to claim 15,

wherein at least said forming said stack of at least sixteen layers and said processing said stack of at least sixteen layers comprise forming a staircase structure,

wherein said staircase structure comprises a portion of connection paths from said peripheral circuits to at least one of said memory cells.

17. The method according to claim 15,

wherein said processing said stack of at least sixteen layers comprises annealing of said first transistors.

18. The method according to claim 15,

wherein each of said memory cells comprises at least one second transistor, said second transistor comprises a source, channel, and drain, and

wherein said source, said channel, and said drain comprise similar doping.

19. The method according to claim 15,

wherein said processing said stack of at least sixteen layers comprises forming metal layers as part of forming connections between said periphery circuits and said memory cells.

20. The method according to claim 15,

wherein said memory cells are part of a non-volatile NAND memory.