Electronic devices and systems, and methods for making and using the same

• US 10,217,668 B2
• Filed: 01/04/2017
• Issued: 02/26/2019
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Thompson, Scott E., Thummalapally, Damodar R.
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US15/398,471
• Publication Number:
  US 20170117366A1
• Time in Patent Office: 783 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element

Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV_T compared to conventional bulk CMOS and can allow the threshold voltage V_T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Claims

1. A field effect transistor (FET) formed in a doped well, the FET having a source, a drain, and a gate stack having a gate length, the FET comprising:

a screening region positioned above the doped well, the screening region being doped with a first type of dopant, the screening region being electrically coupled to the doped well, the screening region being positioned below the gate stack;

a substantially undoped semiconductive layer formed above the screening region, the substantially undoped semiconductive layer being adjacent to the screening region;

a threshold voltage setting region in the substantially undoped semiconductive layer, the threshold voltage setting region being doped with the first type of dopant, the threshold voltage setting region dopant concentration modifying a threshold voltage of the FET;

wherein the gate stack is positioned above the doped well to control conduction between a drain and a source, the source and the drain being doped with a second type of dopant;

wherein at least a portion of the substantially undoped semiconductive layer is maintained as a substantially undoped channel region having a dopant concentration less than 1×

1017 atoms/cm3, with the substantially undoped channel region laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region, and the threshold voltage setting region is vertically positioned between the substantially undoped channel region and the screening region;

wherein the screening region has a dopant concentration greater than ten times the dopant concentration of the substantially undoped channel region and sets a depth of a depletion layer below the gate stack in a direction from the substantially undoped channel region toward the screening region.

2. The FET formed in a doped well according to claim 1, wherein the screening region extends between the drain and the source with constant dopant concentration and respectively contacts the drain and the source.

3. The FET formed in a doped well according to claim 1, wherein the screening region does not contact the drain and the source.

4. The FET formed in a doped well according to claim 1, wherein the undoped channel comprises a layer of which dopant concentration is constant in a depth direction.

5. The FET formed in a doped well according to claim 1, wherein the screening region and the threshold voltage tuning region are doped by same dopant.

6. The FET formed in a doped well according to claim 1, wherein the depletion layer does not go through the screening region, regardless of a voltage of the doped well when a voltage of the gate stack equals to the threshold voltage.