Cascode semiconductor device structure and method therefor

• US 10,217,737 B2
• Filed: 07/12/2017
• Issued: 02/26/2019
• Est. Priority Date: 10/28/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Padmanabhan, Balaji, Venkatraman, Prasad, Hossain, Zia, Liu, Chun-Li, Jeon, Woochul, Mcdonald, Jason
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/648,264
• Publication Number:
  US 20170309617A1
• Time in Patent Office: 594 Days
• Field of Search: 257192
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is configured as a two terminal device.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises a first doped region having a first conductivity type adjacent the second major surface;

a heterostructure adjacent the first major surface, wherein the heterostructure comprises;

a channel layer comprising a group III-V material; and

a barrier layer disposed over the channel layer and comprising a group III-V material;

a first electrode disposed proximate to a first portion of the channel layer;

a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;

a control electrode disposed between the first electrode and the second electrode;

a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the first electrode;

a second trench electrode extending through the heterostructure and the semiconductor substrate at least to the first doped region, wherein the second trench electrode electrically connects the control electrode to a third electrode disposed adjacent to the second major surface, and wherein the control electrode is electrically coupled to the third electrode through the semiconductor substrate; and

a rectifier device comprising a second doped region of a second conductivity type opposite to the first conductivity type disposed adjoining the first trench electrode in the semiconductor substrate, wherein;

the rectifier device is electrically coupled to the first trench electrode and electrically coupled to the third electrode, but not electrically coupled to the second electrode;

the rectifier device is configured to provide a current path generally perpendicular to the channel layer; and

the semiconductor device is configured as a two terminal device.

2. The semiconductor device of claim 1, wherein:

the semiconductor device comprises a group III-V transistor structure;

the first electrode comprises a source electrode;

the second electrode comprises a drain electrode; and

the first electrode overlaps the first trench electrode.

3. The semiconductor device of claim 2, wherein the first trench electrode is inset from at least one side surface of the first electrode.

4. The semiconductor device claim 1, wherein the second doped region and the second electrode overlap.

5. The semiconductor device of claim 1 further comprising a third doped region of the first conductivity type disposed between the semiconductor substrate and the heterostructure.

6. A semiconductor device comprising:

a semiconductor substrate having a first major surface and an opposing second major surface;

a heterostructure adjacent the first major surface, the heterostructure comprising;

a group III-V channel layer; and

a group III-V barrier layer over the group III-V channel layer;

a first electrode disposed proximate to a first portion of the group III-V channel layer;

a second electrode disposed proximate to a second portion of the group III-V channel layer and spaced apart from the first electrode;

a third electrode disposed on the second major surface of the semiconductor substrate;

a control electrode disposed between the first electrode and the second electrode;

a fourth electrode electrically coupled to the first electrode and the semiconductor substrate; and

a rectifier device disposed in the semiconductor substrate and electrically coupled to the fourth electrode and electrically coupled to the third electrode, but not electrically coupled to the second electrode;

the rectifier device is configured to provide a current path generally perpendicular to the channel layer; and

the control electrode is electrically connected to the third electrode through the semiconductor substrate to provide the semiconductor device as a two terminal device.

7. The semiconductor device of claim 6, wherein the rectifier device comprises a first doped region having a first conductivity type and adjoining a lower surface of the fourth electrode, and wherein the semiconductor substrate comprises:

a semiconductor region adjacent the first doped region and comprising a second conductivity type opposite to the first conductivity type; and

a second doped region having the second conductivity type and adjoining the second major surface, wherein the second doped region has a higher dopant concentration than the semiconductor region.

8. The semiconductor device of claim 7, wherein the fourth electrode comprises a first trench electrode extending through the heterostructure, and wherein the control electrode is electrically coupled to the second doped region with a second trench electrode extending through the heterostructure into the semiconductor substrate.

9. The semiconductor device of claim 8 further comprising a third doped region of the second conductivity type disposed adjoining an interface between the heterostructure and the semiconductor substrate.

10. The semiconductor device of claim 8, wherein the heterostructure is devoid of a channel region proximate to the second trench electrode, and wherein the second trench electrode comprises a trench and a conductive electrode.

11. The semiconductor device of claim 10, wherein the second trench electrode further comprises a dielectric material between sidewalls of the trench and the conductive electrode.

12. The semiconductor device of claim 6, wherein:

the rectifier device comprises a Schottky rectifier; and

the third electrode and the second major surface of the semiconductor substrate are configured as a Schottky contact.