Semiconductor device

• US 10,217,759 B2
• Filed: 08/04/2017
• Issued: 02/26/2019
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tsukuda, Eiji, Sonoda, Kenichiro
• Primary Examiner(s): Hargrove, Frederick B
• Application Number:
  US15/669,595
• Publication Number:
  US 20180097007A1
• Time in Patent Office: 571 Days
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a protruding portion which is a portion of the semiconductor substrate, protrudes from an upper surface of the semiconductor substrate, and extends in a first direction along the upper surface of the semiconductor substrate;

a first gate electrode formed over the protruding portion via a first insulating film and extending in a second direction orthogonal to the first direction;

a second gate electrode formed over the protruding portion via a second insulating film including a charge accumulation portion, adjacent to one of side surfaces of the first gate electrode via the second insulating film, and extending in the second direction; and

an n type source region and an n type drain region formed in an upper surface of the protruding portion so as to sandwich, in the first direction, a part of the protruding portion immediately below a pattern having the first gate electrode and the second gate electrode,

wherein the second gate electrode has an upper portion extending across the upper surface of the protruding portion and a lower portion extending along both side surfaces of the protruding portion,

wherein the first gate electrode, the second gate electrode, the source region, and the drain region constitute parts of a nonvolatile memory element, and

wherein an n type impurity concentration of the upper portion of the second gate electrode is lower than an n type impurity concentration of the lower portion of the second gate electrode.

2. The semiconductor device according to claim 1,

wherein the source region has a portion adjacent to the second gate electrode in plan view and comprises:

an n type first semiconductor region;

an n type second semiconductor region having an n type impurity concentration lower than an n type impurity concentration of the first semiconductor region, the n type second semiconductor region being located closer than the first semiconductor region to a part of the protruding portion immediately below the second gate electrode, and being formed along the upper surface and along the side surfaces of the protruding portion; and

an n type third semiconductor region having an n type impurity concentration lower than the n type impurity concentration of the second semiconductor region, the n type third semiconductor region being located closer than the second semiconductor region to a channel region between the source and drain regions, and being formed along the upper surface of the protruding portion.

3. The semiconductor device according to claim 2,

wherein the second semiconductor region has arsenic introduced therein and the third semiconductor region has phosphorus introduced therein.

4. The semiconductor device according to claim 2,

wherein in erase operation of the nonvolatile memory element, data is erased by band-to-band tunneling (BTBT).

5. The semiconductor device according to claim 1,

wherein in erase operation of the nonvolatile memory element, data is erased by Fowler Nordheim (FN) tunneling.

6. The semiconductor device according to claim 1,

wherein a portion of the second gate electrode adjacent to the protruding portion in a direction along the upper surface of the semiconductor substrate has an n type conductivity and a portion of the second gate electrode over the protruding portion has an intrinsic form.

7. The semiconductor device according to claim 1,

wherein the number, per volume, of p type impurities contained in a portion of the second gate electrode adjacent to the protruding portion in a direction along the upper surface of the semiconductor substrate is smaller than the number, per volume, of p type impurities contained in a portion of the second gate electrode over the protruding portion.

8. The semiconductor device according to claim 1,

wherein the second gate electrode comprises:

a first semiconductor layer that covers parts of the side surfaces of the protruding portion and formed below the upper surface of the protruding portion; and

a second semiconductor layer that is formed over the first semiconductor layer and extends across the upper surface of the protruding portion,

wherein the second semiconductor layer has an n type impurity concentration lower than an n type impurity concentration of the first semiconductor layer.

9. The semiconductor device according to claim 1,

wherein in write operation of the nonvolatile memory element, data is written by source side injection (SSI).

10. The semiconductor device according to claim 1,

wherein the n type impurity concentration of the second gate electrode gradually increases from the upper surface of the second gate electrode to a lowermost surface of the second gate electrode.

11. The semiconductor device according to claim 1,

wherein an n type impurity concentration at a lower end of the lower portion of the second gate electrode is higher than the n type impurity concentration of a lower end of the upper portion of the second gate electrode.

12. A semiconductor device, comprising:

a semiconductor substrate;

a protruding portion which is a portion of the semiconductor substrate, protrudes from an upper surface of the semiconductor substrate, and extends in a first direction along the upper surface of the semiconductor substrate;

a first gate electrode formed over an upper surface of the protruding portion via a first insulating film and extending in a second direction orthogonal to the first direction;

a second gate electrode formed over the upper surface of the protruding portion and a side surface of the protruding portion via a second insulating film including a charge accumulation portion, the second gate electrode being adjacent to one of side surfaces of the first gate electrode via the second insulating film, and extending in the second direction; and

an n type source region and an n type drain region formed in the upper surface of the protruding portion so as to sandwich, in the first direction, a part of the protruding portion immediately below a pattern having the first gate electrode and the second gate electrode,

wherein the first gate electrode, the second gate electrode, the source region, and the drain region constitute parts of a nonvolatile memory element, and

wherein the source region has a portion adjacent to the second gate electrode in plan view and comprises;

an n type first semiconductor region;

an n type second semiconductor region having an n type impurity concentration lower than an n type impurity concentration of the first semiconductor region, the n type second semiconductor region being located closer than the first semiconductor region to a part of the protruding portion immediately below the second gate electrode, and being formed along the upper surface and along the side surface of the protruding portion; and

an n type third semiconductor region having an n type impurity concentration lower than an n type impurity concentration of the second semiconductor region, the n type third semiconductor region being located closer than the second semiconductor region to a channel region between the source and drain regions, and being formed along the upper surface of the protruding portion.

13. The semiconductor device according to claim 12,

wherein the second semiconductor region has arsenic introduced therein and the third semiconductor region has phosphorus introduced therein.

14. The semiconductor device according to claim 12,

wherein in erase operation of the nonvolatile memory element, data is erased by band-to-band tunneling (BTBT).

15. The semiconductor device according to claim 12,

wherein in the upper surface of the protruding portion, a formation depth of the third semiconductor region is deeper than a formation depth of the second semiconductor region, and

wherein at the side surface of the protruding portion, a lower end of the third semiconductor region is located above a lower end of the second semiconductor region.