Array substrate and fabrication method thereof, display panel and fabrication method thereof

• US 10,217,773 B2
• Filed: 04/26/2013
• Issued: 02/26/2019
• Est. Priority Date: 02/28/2013
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Jiang, Jingjing, Lee, Gyuhyun, Li, Min, Wang, Song
• Primary Examiner(s): Arendt, Paisley L
• Application Number:
  US14/359,006
• Publication Number:
  US 20150085216A1
• Time in Patent Office: 2,132 Days
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

Embodiments of the disclosure provide an array substrate and a fabrication method thereof, and a display panel and a fabrication method thereof. A passivation layer of the array substrate is made of a black insulation material and the passivation layer is provided with an opening at a pixel display region of the array substrate. The passivation layer is simultaneously used as a black matrix, and thus the aperture ratio of the display panel is effectively increased.

Claims

1. An array substrate, wherein

a passivation layer of the array substrate is made of a black insulation material and the passivation layer is provided with an opening at a pixel display region of the array substrate,

the array substrate comprises a thin film transistor provided below the passivation layer and a pixel electrode provided on the passivation layer,

the passivation layer has a lower surface directly contacting the thin film transistor and an upper surface directly contacting the pixel electrode, and

a thickness of the passivation layer with its lower surface directly contacting the thin film transistor and its upper surface directly contacting the pixel electrode is no less than

2. The array substrate according to claim 1, wherein

the array substrate further comprises a base substrate and a plurality of gate lines and a plurality of data lines that are formed on the base substrate;

the plurality of gate lines and the plurality of data lines intersect with each other to define a plurality of pixel units;

each pixel unit comprises the pixel electrode and the thin film transistor; and

the passivation layer covers the gate line, the data line and the thin film transistor.

3. The array substrate according to claim 1, wherein the optical density of the passivation layer is no less than 4.

4. The array substrate according to claim 3, wherein the optical density is a logarithm of a ratio between a incident light and a transmission light, or is a logarithm of a reciprocal of light transmittance.

5. The array substrate according to claim 1, wherein a relative dielectric constant of the black insulation material is 6-7.

6. A display panel, comprising the array substrate according to claim 1.

7. The display panel according to claim 6, wherein

the display panel further comprises an opposite substrate and a liquid crystal layer provided between the array substrate and the opposite substrate;

and

the opposite substrate does not comprise a black matrix.

8. The display panel according to claim 7, wherein the opposite substrate comprises a base substrate, a color filter layer and a spacer.

9. The display panel according to claim 8, wherein the opposite substrate comprises a protective layer covering an outer surface of the color filter layer.

10. The display panel according to claim 8, wherein the opposite substrate further comprises a transparent conductive layer, and the transparent conductive layer is provided on a side of the base substrate opposite to the color filter layer so as to serve as a shield electrode layer.

11. The display panel according to claim 8, wherein the opposite substrate further comprises a transparent conductive layer, and the transparent conductive layer is provided on the color filter layer to serve as a common electrode layer.

12. The array substrate according to claim 1, wherein the pixel display region corresponds to the pixel electrode.

13. The array substrate according to claim 1, wherein the passivation layer is provided with a via hole at a drain electrode of the thin film transistor.

14. The array substrate according to claim 1, wherein the passivation layer is simultaneously used as a black matrix.

15. The array substrate according to claim 1, wherein the upper surface of the passivation layer is uneven.

16. A fabrication method of an array substrate, comprising:

forming a thin film transistor on a base substrate;

forming a black insulation material film on the thin film transistor, and forming a passivation layer by performing a patterning process on the black insulation material film; and

forming a pixel electrode on the passivation layer, wherein

the passivation layer is provided with an opening at a pixel display region,

the passivation layer has a lower surface directly contacting the thin film transistor and an upper surface directly contacting the pixel electrode, and

a thickness of the passivation layer with its lower surface directly contacting the thin film transistor and its upper surface directly contacting the pixel electrode is no less than

17. The fabrication method of the array substrate according to claim 16, comprising:

forming a gate metal film on the base substrate, and forming a gate electrode and a gate line by performing a patterning process on the gate metal film;

forming a gate insulating layer on the base substrate; and

forming a semiconductor thin film, a doped semiconductor thin film and a source-drain metal film on the base substrate, and forming an active layer, a data line, a source electrode and a drain electrode by performing a patterning process on the semiconductor thin film, the doped semiconductor thin film and the source-drain metal film.

18. The fabrication method of the array substrate according to claim 17, wherein the passivation layer covers the gate line, the data line and the thin film transistor, and the passivation layer is provided with a via hole at a drain electrode of the thin film transistor.