Thin film transistor and manufacturing method thereof, array substrate, and display device

• US 10,217,774 B2
• Filed: 06/16/2017
• Issued: 02/26/2019
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Xie, Zhenyu, Xu, Shaoying, Li, Tiansheng, Yan, Changjiang, Li, Jing, Tian, Zongmin
• Primary Examiner(s): Malsawma, Lex H
• Application Number:
  US15/625,436
• Publication Number:
  US 20170287950A1
• Time in Patent Office: 620 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The technical disclosure relates to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a base substrate, a gate electrode, an active layer, source/drain electrodes, a pixel electrode and one or more insulating layers, wherein at least one of the insulating layers comprises a bottom insulating sub-layer and a top insulating sub-layer, the top insulating sub-layer having a hydrogen content higher than that of the bottom insulating sub-layer.

Claims

1. A method of manufacturing a thin film transistor, comprising:

forming a gate electrode, an active layer, source/drain electrodes, one or more insulating layers and a pixel electrode on a base substrate,

wherein at least one of the insulating layers comprises a silicon oxide sub-layer contacting the active layer and a silicon oxide sub-layer not contacting the active layer, and the silicon oxide sub-layer not contacting the active layer has a hydrogen content higher than that of the silicon oxide sub-layer contacting the active layer, and

wherein the method comprising;

depositing the silicon oxide sub-layer contacting the active layer at 200-300°

C. with a silane gas flow rate of 300-800 sccm and depositing the silicon oxide sub-layer not contacting the active layer at 240-340°

C. with a silane gas flow rate of 600-1200 sccm, in order that the hydrogen content of the silicon oxide sub-layer not contacting the active layer is 5%˜

10%, and the hydrogen content of the silicon oxide sub-layer contacting the active layer is 1%˜

5%.

2. The manufacturing method according to claim 1, wherein

the thin film transistor is an oxide thin film transistor, the at least one of the insulating layers comprises an etch stop layer, and the manufacturing method comprises:

sequentially forming the gate electrode, a gate insulating layer, the active layer, the etch stop layer, the source/drain electrodes, a protective layer, and the pixel electrode on the base substrate, and

a bottom etch stop layer as the silicon oxide sub-layer contacting the active layer and a top etch stop layer as the silicon oxide sub-layer not contacting the active layer are sequentially formed during forming the etch stop layer such that the top etch stop layer has a hydrogen content higher than that of the bottom etch stop layer.

3. The manufacturing method according to claim 2, comprising:

forming the gate electrode on the base substrate;

forming the gate insulating layer covering the base substrate and the gate electrode;

forming the active layer on the gate insulating layer corresponding to the gate electrode;

forming the bottom etch stop layer on the active layer;

forming the top etch stop layer on the bottom etch stop layer;

forming the source/drain electrodes on the top etch stop layer;

forming the protective layer covering the gate insulating layer, the source/drain electrodes and the top etch stop layer; and

forming the pixel electrode on the source/drain electrodes and the protective layer.

4. The manufacturing method according to claim 2, wherein the active layer is made of indium gallium zinc oxide semiconductor or indium zinc oxide semiconductor.

5. The manufacturing method according to claim 2, wherein the active layer is deposited by magnetron sputtering.

6. The manufacturing method according to claim 1, wherein the silicon oxide sub-layer contacting the active layer is deposited at 250°

C. with a silane gas flow rate of 600 sccm;

the silicon oxide sub-layer not contacting the active layer is deposited at 290°

C. with a silane gas flow rate of 900 sccm.

7. The manufacturing method according to claim 1, wherein a thickness of the silicon oxide sub-layer contacting the active layer is smaller than a thickness of the silicon oxide sub-layer not contacting the active layer.

8. The manufacturing method according to claim 1, wherein the silicon oxide sub-layer contacting the active layer is deposited with a thickness of 200-1000 Å

, and the silicon oxide sub-layer not contacting the active layer is deposited with a thickness of 1000-1500 Å

.

9. The manufacturing method according to claim 1, wherein the silicon oxide sub-layer contacting the active layer is deposited with a thickness of 500 Å

, and the silicon oxide sub-layer not contacting the active layer is deposited with a thickness of 1500 Å

.

10. A method of manufacturing a thin film transistor, comprising:

forming a gate electrode, an active layer, source/drain electrodes, one or more insulating layers and a pixel electrode on a base substrate,

wherein at least one of the insulating layers comprises a silicon oxide sub-layer contacting the active layer and a silicon oxide sub-layer not contacting the active layer, and the silicon oxide sub-layer not contacting the active layer has a hydrogen content higher than that of the silicon oxide sub-layer contacting the active layer,

wherein the method comprising;

depositing the silicon oxide sub-layer contacting the active layer at 200-300°

C. with a silane gas flow rate of 300-800 sccm and depositing the silicon oxide sub-layer not contacting the active layer at 240-340°

C. with a silane gas flow rate of 600-1200 sccm, in order that the hydrogen content of the silicon oxide sub-layer not contacting the active layer is 5%˜

10%, and the hydrogen content of the silicon oxide sub-layer contacting the active layer is 1%˜

5%, and

wherein a thickness of the silicon oxide sub-layer contacting the active layer is smaller than a thickness of the silicon oxide sub-layer not contacting the active layer.