Semiconductor device having trenches with enlarged width regions

• US 10,217,830 B2
• Filed: 12/08/2016
• Issued: 02/26/2019
• Est. Priority Date: 12/10/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Ostermann, Thomas, Sorger, Michael
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/373,128
• Publication Number:
  US 20170170286A1
• Time in Patent Office: 810 Days
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a plurality of trenches extending into a semiconductor substrate. Each trench comprises a plurality of enlarged width regions distributed along the trench. At least one electrically conductive trench structure is located in each trench. The semiconductor device comprises an electrically insulating layer arranged between the semiconductor substrate and an electrode structure. The semiconductor device comprises a vertical electrically conductive structure extending through the electrically insulating layer. The vertical electrically conductive structure forms an electrically connection between the electrode structure and an electrically conductive trench structure located in a first trench of at a first enlarged width region. The electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and an electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.

Claims

1. A semiconductor device comprising:

a plurality of trenches extending into a semiconductor substrate, wherein each trench of the plurality of trenches comprises a plurality of enlarged width regions distributed along the trench, and wherein at least one electrically conductive trench structure is located in each trench of the plurality of trenches;

an electrically insulating layer arranged between the semiconductor substrate and a first electrode structure; and

a first vertical electrically conductive structure extending through the electrically insulating layer, wherein the first vertical electrically conductive structure forms an electrical connection between the first electrode structure and an electrically conductive trench structure located in a first trench of the plurality of trenches at a first enlarged width region of the plurality of enlarged width regions of the first trench of the plurality of trenches, and

wherein the electrically insulating layer is arranged between a second enlarged width region of the plurality of enlarged width regions of the first trench and the first electrode structure or a second electrode structure above the second enlarged width region without any vertical electrical connections through the electrically insulating layer at the second enlarged width region.

2. The semiconductor device according to claim 1, wherein a maximum width of the plurality of enlarged width regions is at least 5% larger than a minimum width of the plurality of trenches between two enlarged width regions.

3. The semiconductor device according to claim 1, wherein a minimum width of the plurality of trenches between two enlarged width regions is less than 1 μ

m.

4. The semiconductor device according to claim 1, wherein the plurality of trenches are arranged substantially parallel to each other.

5. The semiconductor device according to claim 1, wherein an average lateral distance between neighboring trenches of the plurality of trenches is less than 2 times a minimum width of the plurality of trenches between two enlarged width regions.

6. The semiconductor device according to claim 1, wherein the electrically insulating layer is arranged adjacently to a surface of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein a first electrically conductive trench structure and a second electrically conductive trench structure are located in each trench of the plurality of trenches,

wherein the first electrically conductive trench structure and the second electrically conductive trench structure are electrically insulated from each other by an electrically insulating material arranged between the first electrically conductive trench structure and the second electrically conductive trench structure.

8. The semiconductor device according to claim 7, wherein a second vertical electrically conductive structure of the first trench is electrically connected to the second electrically conductive trench structure at a third enlarged width region of the first trench.

9. The semiconductor device according to claim 8, wherein the first vertical electrically conductive structure is one of a plurality of first vertical electrically conductive structures electrically connected to the first electrically conductive trench structure located in the first trench, and

wherein the second vertical electrically conductive structure is one of a plurality of second vertical electrically conductive structures electrically connected to the second electrically conductive trench structure located in the first trench.

10. The semiconductor device according to claim 8, wherein a total number of enlarged width regions of the first trench is greater than a number of enlarged width regions comprising first vertical electrically conductive structures electrically connected to the first electrically conductive trench structure located in the first trench and a number of enlarged width regions comprising second vertical electrically conductive structures electrically connected to the second electrically conductive trench structure located in the first trench.

11. The semiconductor device according to claim 8, wherein the first vertical electrically conductive structure of the first trench is electrically connected to the first electrode structure and the second vertical electrically conductive structure of the first trench is electrically connected to the second electrode structure.

12. The semiconductor device according to claim 8, wherein the first vertical electrically conductive structure of the first trench and the second vertical electrically conductive structure of the first trench are electrically connected to the first electrode structure.

13. The semiconductor device according to claim 1, wherein one of the first electrode structure and the second electrode structure is a gate electrode structure, and wherein the other of the first electrode structure and the second electrode structure is a source electrode structure.

14. The semiconductor device according to claim 1, wherein the first trench is located adjacently to a second trench of the plurality of trenches, wherein a first electrically conductive trench structure located in the second trench is electrically connected to the first electrode structure via a first vertical electrically conductive structure of the second trench, and wherein a second electrically conductive trench structure located in the second trench is electrically connected to the second electrode structure via a second vertical electrically conductive structure of the second trench.

15. The semiconductor device according to claim 1, wherein the plurality of trenches comprises at least 10% of all trenches extending into the semiconductor substrate.

16. The semiconductor device according to claim 1, wherein a blocking voltage of the semiconductor device is greater than 10 V.

17. The semiconductor device according to claim 1, wherein:

each trench of the plurality of trenches comprises the plurality of enlarged width regions and a plurality of narrow width regions distributed along the trench in a first lateral direction, and

each of the plurality of enlarged width regions of the plurality of trenches is adjacent, in a second lateral direction, to a narrow width regions of the plurality of narrow width regions of an adjacent trench of the plurality of trenches.

18. The semiconductor device according to claim 1, wherein:

the electrically insulating layer is arranged on the semiconductor substrate between the semiconductor substrate and the first electrode structure, the first electrode structure being disposed on the electrically insulating layer, and

the electrically insulating layer above the second enlarged width region is void of vertical electrical connections such that the first electrode structure or the second electrode structure above the second enlarged width region is vertically insulated from the second enlarged width region of the first trench.

19. The semiconductor device according to claim 8, wherein the second vertical electrically conductive structure forms an electrical connection between a second electrode structure, disposed on the electrically insulating layer, and the second electrically conductive trench structure.