Semiconductor structure with multiple transistors having various threshold voltages

• US 10,217,838 B2
• Filed: 04/26/2018
• Issued: 02/26/2019
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Zhao, Dalong, Bakhishev, Teymur, Scudder, Lance, Gregory, Paul E., Duane, Michael, Sridharan, U. C., Ranade, Pushkar, Shifren, Lucian, Hoffmann, Thomas
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/963,598
• Publication Number:
  US 20180261683A1
• Time in Patent Office: 306 Days
• Field of Search: 257288, 257392, 257369, 438527, 438197, 438481, 438308
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Claims

1. A method of fabricating a semiconductor structure, comprising:

implanting in a substrate a first antipunchthrough region for a transistor element;

implanting in the substrate a second antipunchthrough region for the transistor element;

implanting in the substrate a first screening region for the transistor element with a first dopant species;

implanting in the substrate a second screening region for the transistor element with a second dopant species different from the first dopant species;

forming a substantially undoped epitaxial layer covering the first and the second screening regions to form a channel layer for the transistor element, and

wherein the first dopant species and the second dopant species are of same polarity;

the second anitpunchthrough region is located under the first screening region and the second screening region, the first antipunchthrough region is located under the second antipunchthrough region.

2. The method of claim 1, wherein the second dopant species is a heavier molecule than the first dopant species.

3. The method of claim 1, wherein the first dopant species diffuses more than the second dopant species.

4. The method of claim 1, wherein the first screening region at least partially overlaps with the second screening region in the depth direction.

5. The method of claim 1, wherein the second screening region is shallower than the first screening region.

6. The method of claim 1, wherein the first dopant species is B, the second dopant species is BF2 for an NMOS transistor.

7. The method of claim 1, wherein the first dopant species is As, the second dopant species is Sb for an PMOS transistor.

8. The method of claim 1, wherein the second antipunchthrough region at least partially overlaps with the first screening region in the depth direction.

9. The method of claim 1, wherein the first antipunchthrough region at least partially overlaps with the second antipunchthrough region in the depth direction.