Semiconductor device and its manufacturing method

• US 10,217,872 B2
• Filed: 06/17/2017
• Issued: 02/26/2019
• Est. Priority Date: 08/31/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kawashima, Yoshiyuki, Inoue, Masao, Yoshitomi, Atsushi
• Primary Examiner(s): Gumedzoe, Peniel M
• Assistant Examiner(s): Johnson, Christopher A
• Application Number:
  US15/626,092
• Publication Number:
  US 20180061997A1
• Time in Patent Office: 619 Days
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.

Claims

1. A semiconductor device having a memory cell comprising:

in a first region of a first conductive type semiconductor substrate,

a plurality of first projection units, which are a part of the semiconductor substrate, and extend in a first direction along a main surface of the semiconductor substrate;

a first gate electrode, which is formed over an upper surface and a sidewall of the first projection units through a first insulating film, and extends in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate;

a second gate electrode, which is formed adjacent to one side surface of the first gate electrode, and extends in the second direction;

a second insulating film, which is formed between the first gate electrode and the second gate electrode and between the first projection units and the second gate electrode, and includes a charge accumulation film; and

first source/drain regions, which are of a second conductive type different from the first conductive type, and are formed in the first projection units at a position on a side of the first gate electrode that is opposite the second gate electrode in the first direction and in the first projection units at a position on a side of the second gate electrode that is opposite the first gate electrode in the first direction,

wherein the first gate electrode and the second gate electrode are formed from polycrystalline silicon, which is of the second conductive type,

wherein a first metal film is provided between the first insulating film and the first gate electrode, and a second metal film is provided between the second insulating film and the second gate electrode,

wherein a first work function of the first metal film and a second work function of the second metal film are different from each other,

wherein the first conductive type is p-type, and the second conductive type is n-type,

wherein the first work function is greater than the second work function,

wherein the first metal film and the second metal film are formed of titanium nitride, and

wherein a thickness of the first metal film is greater than a thickness of the second metal film.

2. The semiconductor device according to claim 1,

wherein the thickness of the first metal film is equal to or greater than 5 nm and equal to or less than 50 nm.

3. The semiconductor device according to claim 1, having a transistor comprising:

in a second region different from the first region of the semiconductor substrate,

a plurality of second projection units, which are a part of the semiconductor substrate, and extend in a third direction along the main surface of the semiconductor substrate;

a third gate electrode, which is formed over an upper surface and a sidewall of the second projection units through a third insulating film, and extends in a fourth direction orthogonal to the third direction along the main surface of the semiconductor substrate; and

second source/drain regions, which are formed in the second projection units at positions on both sides of the third gate electrode in the third direction,

wherein the third insulating film is an insulating film whose dielectric constant is higher than that of SiO₂, and

wherein the third gate electrode includes metal.

4. A semiconductor device comprising:

a semiconductor substrate having a main surface, a plurality of first projections extending in a first direction along the main surface, and a first conductivity type;

a first insulating film formed on the first projections;

a first metal film formed on the first insulating film;

a first gate electrode formed on the first metal film;

a second gate electrode formed over the first projections and adjacent to the first gate electrode;

a second insulating film formed between the first projections and the second gate electrode, and between the first and second gate electrodes, the second insulating film including a charge accumulation film;

a second metal film formed between the second gate electrode and the second insulating film; and

a pair of source/drain regions formed in the first projections such that the first and second gate electrodes are between the pair of source/drain regions in plan view, and having a second conductivity type different from the first conductivity type,

wherein the first and second gate electrodes are formed of polycrystalline silicon having the second conductivity type,

wherein a work function of the first metal film is different than a work function of the second metal film, and

wherein a thickness of the first metal film is different than a thickness of the second metal film.

5. The semiconductor device according to claim 4, wherein the first metal film is formed of a same material as the second metal film.

6. The semiconductor device according to claim 5, wherein the first metal film and the second metal film are formed of titanium nitride.

7. The semiconductor device according to claim 6,

wherein the first conductivity type is p-type, and the second conductivity type is n-type, and

the thickness of the first metal film is greater than the thickness of the second metal film.

8. The semiconductor device according to claim 7, wherein the thickness of the first metal film is between 5 nm and 50 nm, inclusive.

9. The semiconductor device according to claim 6,

wherein the first conductivity type is n-type, and the second conductivity type is p-type, and

the thickness of the first metal film is less than a thickness of the second metal film.

10. The semiconductor device according to claim 9, wherein the thickness of the first metal film is between 1 nm and 5 nm, inclusive.