ECC memory controller supporting secure and non-secure regions

• US 10,218,387 B2
• Filed: 05/08/2017
• Issued: 02/26/2019
• Est. Priority Date: 05/08/2017
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: David, Thomas S.
• Primary Examiner(s): Vallecillo, Kyle
• Application Number:
  US15/589,199
• Publication Number:
  US 20180323808A1
• Time in Patent Office: 659 Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

Claims

1. A system supporting memory with secure and non-secure regions, comprising:

an ECC memory controller adapted to communicate with a data memory and an ECC memory;

a secure mode signal in communication with the ECC memory controller;

wherein the ECC memory controller generates a first syndrome to be written to the ECC memory for a first data word if the secure mode signal is a first value and generates a second syndrome, different than the first syndrome, to be written to the ECC memory for the first data word if the secure mode signal is a second value.

2. The system of claim 1, wherein the ECC memory controller comprises a write logic block, the write logic block comprising a syndrome generator to generate the first syndrome for the first data word, and a syndrome modifier function, wherein the syndrome modifier function generates the second syndrome for the first data word.

3. The system of claim 2, wherein the syndrome modifier function receives the first syndrome as an input, and generates the second syndrome.

4. The system of claim 2, wherein the syndrome modifier function receives the first data word as an input, and generates the second syndrome.

5. The system of claim 2, further comprising a multiplexor having the first syndrome, the second syndrome and the secure mode signal as inputs, wherein the multiplexor selects the first syndrome or the second syndrome to write to the ECC memory based on a value of the secure mode signal.

6. The system of claim 1, wherein the ECC memory controller computes a calculated syndrome for a second data word read from the data memory, and compares the calculated syndrome to an ECC syndrome read from the ECC memory if the secure mode signal is the first value and computes a modified calculated syndrome, different than the calculated syndrome, for the second data word, and compares the modified calculated syndrome to the ECC syndrome read from the ECC memory if the secure mode signal is the second value.

7. The system of claim 6, wherein the ECC memory controller indicates an ECC error if, when the secure mode signal is the first value, the ECC syndrome read from the ECC memory does not match the calculated syndrome.

8. The system of claim 7, wherein the ECC memory controller indicates an ECC error if, when the secure mode signal is the second value, the ECC syndrome read from the ECC memory does not match the modified calculated syndrome.

9. The system of claim 7, wherein the ECC memory controller indicates an ECC error if, when the secure mode signal is the second value, the ECC syndrome read from the ECC memory does not match the calculated syndrome and does not match the modified calculated syndrome.

10. The system of claim 6, wherein the ECC memory controller comprises a read logic block, comprising a syndrome generator to compute the calculated syndrome based on the second data word read from the data memory, a syndrome modifier function to compute the modified calculated syndrome and a comparator, wherein the comparator receives the secure mode signal as an input, and compares the ECC syndrome read from the ECC memory to the calculated syndrome and the modified calculated syndrome based on a value of the secure mode signal.

11. The system of claim 1, wherein the ECC memory controller computes a calculated syndrome for a second data word read from the data memory, and compares the calculated syndrome to an ECC syndrome read from the ECC memory if the secure mode signal is the first value and computes a modified ECC syndrome from the ECC syndrome read from the ECC memory, and compares the calculated syndrome to the modified ECC syndrome if the secure mode signal is the second value.

12. The system of claim 11, wherein the ECC memory controller indicates an ECC error if, when the secure mode signal is the first value, the ECC syndrome read from the ECC memory does not match the calculated syndrome.

13. The system of claim 12, wherein the ECC memory controller indicates an ECC error if, when the secure mode signal is the second value, the modified ECC syndrome does not match the calculated syndrome.

14. The system of claim 12, wherein the ECC memory controller indicates an ECC error if, when the secure mode signal is the second value, the calculated syndrome does not match the ECC syndrome read from the ECC memory and does not match the modified ECC syndrome.

15. The system of claim 11, wherein the ECC memory controller comprises a read logic block, comprising a syndrome generator to compute the calculated syndrome based on the second data word read from the data memory, a syndrome modifier function to compute the modified calculated syndrome based on the ECC syndrome read from the ECC memory and a comparator, wherein the comparator receives the secure mode signal as an input, and compares the calculated syndrome to the ECC syndrome read from the ECC memory and the modified ECC syndrome based on a value of the secure mode signal.

16. A method of partitioning a memory, having a data memory and an ECC memory, into secure and non-secure regions, comprising:

calculating a first ECC syndrome to be written with a data word if a secure mode signal is asserted first value; and

calculating a second ECC syndrome, different from the first ECC syndrome to be written with the data word if the secure mode signal is asserted second value; and

writing the first ECC syndrome or the second ECC syndrome to the ECC memory, based on a value of the secure mode signal, when the data word is written to the data memory.

17. The method of claim 16, wherein a write logic block, disposed within an ECC memory controller, generates the first ECC syndrome for the data word using a syndrome generator and generates the second ECC syndrome for the data word using a syndrome modifier function.

18. The method of claim 17, wherein the syndrome modifier function receives the first ECC syndrome as an input, and generates the second ECC syndrome.

19. The method of claim 17, wherein the syndrome modifier function receives the data word as an input, and generates the second ECC syndrome.

20. The method of claim 16, further comprising:

computing a calculated syndrome for the data word when the data word is read from the data memory;

comparing the calculated syndrome to an ECC syndrome read from the ECC memory if the secure mode signal is the first value;

computing a modified calculated syndrome, different than the calculated syndrome, for the data word; and

comparing the modified calculated syndrome to the ECC syndrome read from the ECC memory if the secure mode signal is the second value.

21. The method of claim 20, further comprising indicating an ECC error if, when the secure mode signal is the first value, the ECC syndrome read from the ECC memory does not match the calculated syndrome.

22. The method of claim 21, further comprising indicating an ECC error if, when the secure mode signal is the second value, the ECC syndrome read from the ECC memory does not match the modified calculated syndrome.

23. The method of claim 21, further comprising indicating an ECC error if, when the secure mode signal is the second value, the ECC syndrome read from the ECC memory does not match the calculated syndrome and does not match the modified calculated syndrome.

24. The method of claim 16, further comprising:

computing a calculated syndrome for the data word read from the data memory;

comparing the calculated syndrome to an ECC syndrome read from the ECC memory if the secure mode signal is the first value;

computing a modified ECC syndrome from the ECC syndrome read from the ECC memory; and

comparing the calculated syndrome to the modified ECC syndrome if the secure mode signal is the second value.

25. The method of claim 24, further comprising indicating an ECC error if, when the secure mode signal is the first value, the ECC syndrome read from the ECC memory does not match the calculated syndrome.

26. The method of claim 25, further comprising indicating an ECC error if, when the secure mode signal is the second value, the modified ECC syndrome does not match the calculated syndrome.

27. The method of claim 25, further comprising indicating an ECC error if, when the secure mode signal is the second value, the calculated syndrome does not match the ECC syndrome read from the ECC memory and does not match the modified ECC syndrome.

28. A system supporting memory with secure and non-secure regions, comprising:

an ECC memory controller adapted to communicate with a data memory and an ECC memory; and

a secure mode signal in communication with the ECC memory controller;

wherein the ECC memory controller;

reads a data word from the data memory and an ECC syndrome from the ECC memory;

performs a first comparison if the secure mode signal is a first value and indicates an ECC error if the first comparison fails; and

performs a second comparison if the secure mode signal is a second value and indicates an ECC error if the second comparison fails.

29. The system of claim 28, wherein the first comparison comprises computing a calculated syndrome based on the data word and comparing the calculated syndrome to the ECC syndrome.

30. The system of claim 29, wherein the second comparison comprises computing a modified syndrome based on the data word and comparing the modified syndrome to the ECC syndrome.

31. The system of claim 29, wherein the second comparison comprises computing a modified syndrome based on the ECC syndrome and comparing the modified syndrome to the calculated syndrome.