Integrated mixed-signal ASIC with DAC and DSP

• US 10,218,430 B2
• Filed: 11/14/2016
• Issued: 02/26/2019
• Est. Priority Date: 08/15/2014
• Status: Active Grant

• Current Assignee: SEAKR Engineering, Inc. (Rtx Corporation)
• Original Assignee: SEAKR Engineering, Inc. (Rtx Corporation)
• Inventors: Buehler, Erik, Van Buren, Damon, Rutt, Paul
• Primary Examiner(s): Tse, Young T
• Application Number:
  US15/351,224
• Publication Number:
  US 20170063446A1
• Time in Patent Office: 834 Days
• Field of Search: 375316, 375320, 375322, 375324, 375326-328, 375340, 375344, 375345, 341 61, 341108, 341110, 341128, 341129, 341144, 341155, 341159, 710 3, 710 4, 710 69- 71
• CPC Class Codes: H04B 1/0039 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/0042 Digital filtering H04B1/0035 takes precedence; digital filters per se H03H17/00
• CPC Class Codes: H04B 1/0046 Decimation, i.e. data rate reduction techniques
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 7/08 at the receiving station
• CPC Class Codes: H04B 7/1851 Systems using a satellite or space-based relay H04B7/18508, H04B7/18521 take precedence; providing specific services H04B7/18523 - H04B7/18576
• CPC Class Codes: H04B 7/18515 Transmission equipment in satellites or space-based relays
• CPC Class Codes: H04B 7/212 Time-division multiple access [TDMA]

Abstract

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuity is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

Claims

1. An integrated digital to analog converting RF transmitter implemented in a satellite, comprising:

a plurality of radiation tolerant high speed digital to analog converters (DACs) units, which each receive a sampled digital signal and output an RF signal;

a plurality of radiation tolerant digital inputs; and

one or more radiation tolerant digital signal processing (DSP) cores, which each process data from one or more of the radiation tolerant digital inputs and output the processed data to at least one radiation tolerant high speed DAC;

wherein one or more of the radiation tolerant high speed DACs, the one or more of the radiation tolerant digital inputs, and/or the one or more radiation tolerant DSP cores have been determined, by testing, to be radiation tolerant and have a heavy ion cross section less than or equal to 10<sup>−

4</sup> cm² (square centimeters) at a linear energy transfer greater than or equal to 37 MeV-cm²/mg (mega-electronVolts-square centimeters per milligram).

2. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter provides an output from the one or more radiation tolerant DSP cores to the one or more of the radiation tolerant high speed DACs.

3. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the one or more radiation tolerant DSP cores are configured to:

perform, by a digital mixer of the one or more radiation tolerant DSP cores, a frequency translation of data from baseband to RF; and

suppress, by a decimating filter of the one or more radiation tolerant DSP cores, images while upsampling a baseband signal to an output sample rate prior to frequency upconversion, and to reduce an input sample rate.

4. The integrated RF transmitter implemented in the satellite according to claim 3, wherein the one or more radiation tolerant DSP cores are further configured to perform a digital frequency synthesis, wherein the digital frequency synthesis includes:

storing, in a lookup table (LUT) of the one or more radiation tolerant DSP cores, a sampled sinusoid, including a plurality of sampled values; and

encoding, by a digital phase accumulator of the one or more radiation tolerant DSP cores, a phase by mapping to one of the sampled values;

wherein a digitized sample is produced by the digital phase accumulator by stepping through the sampled values.

5. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the one or more radiation tolerant DSP cores are configured to provide:

a cascade of interpolating frequency translating filtering that hierarchically upconverts and upsamples digital data to feed at least one of the radiation tolerant high speed DACs.

6. The integrated RF transmitter implemented in the satellite according to claim 1, further comprising a digital tune frequency input associated with the one or more radiation tolerant DSP cores for rapidly changing a frequency of the data during operation of the RF transmitter.

7. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter further comprises a digital bandwidth selection input for rapidly changing a processing bandwidth of the one or more radiation tolerant DSP cores, which correspond to an interpolation ratio.

8. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter further comprises a time-division multiple access (TDMA) time slot power activation-deactivation time synchronization input associated with the one or more radiation tolerant DSP cores configured to save power of the one or more radiation tolerant DSP cores when operating during an inactive portion of a TDMA frame.

9. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the radiation tolerant digital inputs include configurable complex floating point data conversion configured to conserve digital data input communication bandwidth while preserving data fidelity regardless of an interpolation ratio.

10. The integrated RF transmitter implemented in the satellite according to claim 9, wherein the configurable complex floating point data conversion includes receiving complex numbers that include i and q portions (in-phase and quadrature portions) that share one or more bits related to exponents thereof.

11. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter further comprises radiation hardened flip flops associated with the one or more radiation tolerant DSP cores in place of configuration and other registers configured to ensure operation of the one or more radiation tolerant DSP cores in a space environment with a low error rate.

12. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter is implemented on a single monolithic silicon device.

13. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter is implemented on an Application Specific Integrated Circuit (ASIC).

14. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter is implemented on a multi-chip module.

15. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter is implemented on a hybrid integrated circuit device.

16. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter selectively disables unused radiation tolerant digital inputs when processing less than a maximum bandwidth of the integrated RF transmitter.

17. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the RF transmitter utilizes flexible data unpacking of data from the radiation tolerant digital inputs.

18. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the plurality of radiation tolerant high speed DACs, the plurality of radiation tolerant digital inputs, and the one or more radiation tolerant DSP cores have each been determined to be radiation tolerant by radiation tests comprising:

directing a beam of charged particles from a particle accelerator onto each of the radiation tolerant high speed DACs, the one or more radiation tolerant DSP cores, and the radiation tolerant digital inputs; and

determining, for each radiation tolerant high speed DAC, each radiation tolerant DSP core, and each radiation tolerant digital input, one or more of;

the number of radiation induced single event upsets (SEU), radiation induced single event transients (SET), and radiation induced single event functional interrupts (SEFI).

19. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the one or more of the radiation tolerant high speed DACs, the one or more of the radiation tolerant digital outputs, and/or the one or more of the radiation tolerant DSP cores are radiation hard by design (RHBD) or radiation hard by process (RHBP) to mitigate at least one of:

a single event latchup (SEL), a single event upset (SEU), a single event transient (SET), and a single event functional interrupt (SEFI).

20. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the plurality of radiation tolerant high speed DACs, the plurality of radiation tolerant digital inputs, and the one or more radiation tolerant reconfigurable DSP cores of the RF transmitter are contained in a single package.

21. The integrated RF transmitter implemented in the satellite according to claim 1, wherein the one or more radiation tolerant reconfigurable DSP cores are configured to perform one or more of channelization by a channelizer, reconstruction by a reconstructor, and/or beamforming by a beamformer.

22. An integrated digital to analog converting RF transmitter implemented in a satellite, comprising:

a plurality of radiation tolerant high speed digital to analog converters (DACs), which each receive a sampled digital signal and output an RF signal;

a plurality of radiation tolerant digital inputs; and

one or more radiation tolerant reconfigurable digital signal processing (DSP) cores, which each DSP core processes data from one or more of the radiation tolerant digital inputs and output the processed data to at least one radiation tolerant high speed DAC;

wherein the RF transmitter is implemented in the satellite and one or more of the radiation tolerant high speed DACs, one or more of the radiation tolerant digital inputs, and/or the one or more radiation tolerant reconfigurable DSP cores are radiation hard by design (RHBD) or radiation hard by process (RHBP) to mitigate at least one of single event latchup (SEL), single event upset (SEU), single event transient (SET), and single event functional interrupt (SEFI) radiation effects;

wherein the plurality of radiation tolerant high speed DACs, the plurality of radiation tolerant digital inputs, and the one or more radiation tolerant reconfigurable DSP cores are integrated on a single monolithic silicon device.

23. The integrated RF transmitter implemented in the satellite according to claim 22, wherein RHBD or RHBP mitigation is determined by testing and/or analysis of the one or more of the radiation tolerate high speed DACs, the one or more of the radiation tolerant digital inputs, and/or the one or more of the radiation tolerant reconfigurable DSP cores.

24. The integrated RF transmitter implemented in the satellite according to claim 22, wherein mitigation of the SEL, SEU, SET, and SEFI radiation effects is performed spatially and/or temporally close to the source of the SEL, SEU, SET, or SEFI.

25. The integrated RF transmitter implemented in the satellite according to claim 22, wherein the plurality of radiation tolerant high speed DACs, the plurality of radiation tolerant digital inputs, and the one or more radiation tolerant reconfigurable DSP cores of the RF transmitter are contained in a single package.

26. The integrated RF transmitter implemented in the satellite according to claim 22, wherein the one or more radiation tolerant reconfigurable DSP cores are configured to perform one or more of channelization by a channelizer, reconstruction by a reconstructor, and/or beamforming by a beamformer.

27. An integrated digital to analog converting RF transmitter implemented in a satellite, comprising:

a plurality of radiation tolerant high speed digital to analog converters (DACs), which each receive a sampled digital signal and output an RF signal;

a plurality of radiation tolerant digital inputs; and

one or more radiation tolerant reconfigurable digital signal processing (DSP) cores, which each process data from one or more of the radiation tolerant digital inputs and output the processed data to at least one radiation tolerant high speed DAC;

wherein the plurality of radiation tolerant high speed DACs, the plurality of radiation tolerant digital inputs, and the one or more radiation tolerant reconfigurable DSP cores are integrated and contained on one die or a plurality of die all located in a single package, and at least one of the radiation tolerant high speed DACs, the plurality of radiation tolerant digital inputs, and/or the one or more radiation tolerant reconfigurable DSP cores have been determined, by testing or analysis, to be radiation tolerant.

28. The integrated RF transmitter implemented in the satellite according to claim 27, wherein at least one of the radiation tolerant reconfigurable DSP cores is configured to perform at least beamforming, channelization, and reconstruction.