Method and circuit for low voltage current-mode bandgap

• US 10,222,817 B1
• Filed: 09/29/2017
• Issued: 03/05/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Deng, JingDong
• Primary Examiner(s): Cox, Cassandra
• Application Number:
  US15/721,236
• Time in Patent Office: 522 Days
• Field of Search: None
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: H03L 3/00 Starting of generators

Abstract

A bandgap reference (BGR) circuit and method generates a constant voltage reference that is stable over temperature variations. The BGR circuit is composed of a proportional to absolute temperature (PTAT) stage, a complementary to absolute temperature (CTAT) stage, and an output stage interposed between the PTAT stage and the CTAT stage. The PTAT stage is configured to produce a PTAT current and the CTAT stage is configured to produce a CTAT current. The BGR circuit is configured to mirror the PTAT current and mirror the CTAT current to produce a mirrored PTAT current and a mirrored CTAT current in the output stage and the output stage is configured to combine the mirrored PTAT current and the mirrored CTAT current to generate the constant voltage reference.

Claims

1. A circuit for generating a constant voltage reference, the circuit comprising:

a proportional to absolute temperature (PTAT) stage configured to produce a PTAT current;

a complementary to absolute temperature (CTAT) stage configured to produce a CTAT current;

an output stage interposed between the PTAT stage and the CTAT stage, the circuit configured to mirror the PTAT current and mirror the CTAT current to produce a mirrored PTAT current and a mirrored CTAT current in the output stage, the output stage configured to combine the mirrored PTAT current and the mirrored CTAT current to generate the constant voltage reference; and

a start-up circuit coupled to the PTAT stage, the start-up circuit configured to cause a flow of current in the circuit and to shut down, automatically, in response to the flow.

2. The circuit of claim 1, wherein circuit elements of the circuit are composed of a silicon material and the constant voltage generated is independent of temperature and no greater than a bandgap voltage of the silicon material.

3. The circuit of claim 1, wherein the output stage includes a resistor and the constant voltage reference is constant across the resistor and is independent of temperature.

4. The circuit of claim 1, wherein the PTAT stage includes an operational amplifier, wherein the start-up circuit is coupled to an output terminal of the operational amplifier, and wherein the start-up circuit is configured to sense the output terminal of the operational amplifier and couple the output to a ground reference to cause the flow of current in the circuit.

5. The circuit of claim 1, wherein the circuit further comprises a first current mirror and a second current mirror, the first current mirror configured to mirror the PTAT current and the second current mirror configured to mirror the CTAT current.

6. The circuit of claim 5, wherein:

the first current mirror is composed of a first p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second p-channel MOSFET included in the PTAT stage and a third p-channel MOSFET included in the output stage;

the second current mirror is composed of a fourth p-channel MOSFET included in the output stage and a fifth p-channel MOSFET in the CTAT stage; and

the third p-channel MOSFET and the fourth p-channel MOSFET are configured in parallel in the output stage.

7. The circuit of claim 5, wherein:

the PTAT stage is composed of the first p-channel MOSFET, the second p-channel MOSFET, an operational amplifier, a resistor, a first diode, and a second diode;

an output terminal of the operational amplifier is coupled to a first gate of the first p-channel MOSFET and a second gate of the second p-channel MOSFET;

a negative input terminal of the operational amplifier is coupled to the first p-channel MOSFET, the first diode, and a first drain of the first p-channel MOSFET;

a positive input terminal of the operational amplifier is coupled to the second p-channel MOSFET, the resistor, and a second drain of the second p-channel MOSFET; and

the resistor is coupled to the second diode.

8. The circuit of claim 1, wherein:

the CTAT stage is composed of a p-channel MOSFET, an operational amplifier, and a resistor;

the resistor is coupled to a drain of the p-channel MOSFET;

the drain is coupled to a positive input terminal of the operational amplifier; and

a negative input terminal of the operational amplifier is coupled to the PTAT stage and an output terminal of the operational amplifier is coupled to a gate of the p-channel MOSFET.

9. The circuit of claim 1, wherein:

the PTAT stage includes a first operational amplifier with a first negative input terminal;

the CTAT stage includes a second operational amplifier with a second negative input terminal; and

the first negative input terminal is coupled to the second negative input terminal.

10. The circuit of claim 9, wherein the PTAT stage further includes a p-channel MOSFET and a diode and the first negative input terminal is coupled further to the p-channel MOSFET and the diode.

11. A method for generating a constant voltage reference, the method comprising:

coupling a start-up circuit to a proportional to absolute temperature (PTAT) stage of a circuit;

causing a flow of current in the circuit via the start-up circuit;

shutting down the start-up circuit, automatically, in response to the flow;

producing a PTAT current in the PTAT stage;

producing a complementary to absolute temperature (CTAT) current in a CTAT stage of the circuit;

mirroring the PTAT current and mirroring the CTAT current in an output stage of the circuit to produce a mirrored PTAT current and a mirrored CTAT current in the output stage, the output stage interposed between the PTAT stage and the CTAT stage; and

combining the mirrored PTAT current and the mirrored CTAT current in the output stage to generate the constant voltage reference.

12. The method of claim 11, wherein circuit elements of the circuit are composed of a silicon material and the constant voltage generated is independent of temperature and no greater than a bandgap voltage of the silicon material.

13. The method of claim 11, wherein the circuit includes a resistor in the output stage and wherein the constant voltage reference is constant across the resistor and is independent of temperature.

14. The method of claim 11, wherein the circuit includes an operational amplifier in the PTAT stage, wherein the coupling includes coupling the start-up circuit to an output terminal of the operational amplifier, and wherein the method further comprises:

sensing the output terminal of the operational amplifier by the start-up circuit and coupling the output to a ground reference by the start-up circuit in response to the sensing to cause the flow of current in the circuit.

15. The method of claim 11, wherein the circuit includes a first current mirror and a second current mirror and wherein the method further comprises mirroring the PTAT current via the first current mirror and mirroring the CTAT current via the second current mirror.

16. The method of claim 15, wherein the method further comprises:

forming the first current mirror via a first p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a second p-channel MOSFET included in the PTAT stage and a third p-channel MOSFET included in the output stage;

forming the second current mirror via a fourth p-channel MOSFET included in the output stage and a fifth p-channel MOSFET in the CTAT stage; and

configuring the third p-channel MOSFET and the fourth p-channel MOSFET, in parallel, in the output stage.

17. The method of claim 15, wherein the PTAT stage includes the first p-channel MOSFET, the second p-channel MOSFET, an operational amplifier, a resistor, a first diode, and a second diode, and wherein the method further comprises:

coupling an output terminal of the operational amplifier to a first gate of the first p-channel MOSFET and a second gate of the second p-channel MOSFET;

coupling a negative input terminal of the operational amplifier to the first p-channel MOSFET, the first diode, and a first drain of the first p-channel MOSFET;

coupling a positive input terminal of the operational amplifier to the second p-channel MOSFET, the resistor, and a second drain of the second p-channel MOSFET; and

coupling the resistor to the second diode.

18. The method of claim 11, wherein the CTAT stage includes a p-channel MOSFET, an operational amplifier, and a resistor, and wherein the method further comprises:

coupling the resistor to a drain of the p-channel MOSFET;

coupling the drain to a positive input terminal of the operational amplifier;

coupling a negative input terminal of the operational amplifier to the PTAT stage; and

coupling an output terminal of the operational amplifier to a gate of the p-channel MOSFET.

19. The method of claim 11, wherein the PTAT stage includes a first operational amplifier with a first negative input terminal, the CTAT stage includes a second operational amplifier with a second negative input terminal, and wherein the method further comprises coupling the first negative input terminal to the second negative input terminal.

20. The method of claim 19, wherein the PTAT stage further includes a p-channel MOSFET and a diode and wherein the method further comprises coupling the first negative input terminal further to the p-channel MOSFET and the diode.