Compare-and-swap transaction

• US 10,223,002 B2
• Filed: 02/08/2017
• Issued: 03/05/2019
• Est. Priority Date: 02/08/2017
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Mannava, Phanindra Kumar, Mathewson, Bruce James, Bruce, Klas Magnus, Lacourba, Geoffray Matthieu
• Primary Examiner(s): Nguyen, Hiep T
• Application Number:
  US15/427,335
• Publication Number:
  US 20180225047A1
• Time in Patent Office: 755 Days
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. The compare data value is packed into a first region of the data field in dependence of an offset portion of the target address and having a position within the data field corresponding to the position of the target data value within the storage location. This reduces latency and circuitry required at the processing unit for handling the compare and swap transaction.

Claims

1. An apparatus comprising:

a master device to issue a transactions specifying a target address and comprising a data field for transporting at least one operand value, wherein the master device is configured to issue a compare-and-swap transaction for which said at least one operand value comprises a compare data value and a swap data value; and

a processing unit responsive to the compare-and-swap transaction to select whether to write the swap data value to a storage location corresponding to the target address in dependence on whether the compare data value matches a target data value read from the storage location, an offset portion of the target address indicating the position of the target data value within the storage location;

wherein when issuing the compare-and-swap transaction, the master device is configured to pack the compare data value into a first region of said data field selected in dependence on said offset portion of the target address and having a position within said data field corresponding to the position of the target data value within the storage location.

2. The apparatus according to claim 1, wherein the master device is configured to pack the swap data value into a second region of said data field adjacent to said first region.

3. The apparatus according to claim 2, wherein the first region and the second region form a combined portion of the data field starting at an offset within said data field corresponding to a multiple of a size of said combined portion.

4. The apparatus according to claim 1, wherein when the target address is aligned with respect to a multiple of a combined size of said compare data value and said swap data value, the master device is configured to pack the swap data value into a second region following the first region in the data field;

and

when the target address is misaligned with respect to a multiple of said combined size, the master device is configured to pack the swap data value into a second region preceding the first region in the data field.

5. The apparatus according to claim 1, wherein the processing unit comprises an arithmetic logic unit to perform a compare operation on the compare data value extracted from the data field and the target data value read from the storage location.

6. The apparatus according to claim 5, wherein in the compare operation, the arithmetic logic unit is configured to receive as one of its input operands an unshifted version of the data field of the compare-and-swap transaction.

7. The apparatus according to claim 5, wherein the processing unit comprises a shifter to perform a shift operation to shift the data field to align the swap data value with the position of the target data value within the storage location.

8. The apparatus according to claim 7, wherein the shifter is configured to perform the shift operation in parallel with the arithmetic logic unit performing the compare operation.

9. The apparatus according to claim 1, wherein the master device is configured to issue at least one other type of transaction for which said data field comprises a single operand data value, and the processing unit is responsive to said at least one other type of transaction to update the storage location corresponding to the target address with a value dependent on at least said single operand data value;

wherein for said at least one other type of transaction, the master device is configured to pack said single operand data value into said first region of said data field.

10. The apparatus according to claim 9, wherein the processing unit comprises an arithmetic logic unit to generate a value to be written to the storage location in response to a given transaction, and a mapping between said data field of the given transaction and one of the inputs to the arithmetic logic unit is the same for both said compare-and-swap transaction and said at least one other type of transaction.

11. The apparatus according to claim 1, wherein said transactions comprising said data field comprises an atomic transactions for controlling the processing unit to perform an indivisibly observed set of operations.

12. The apparatus according to claim 1, comprising a plurality of master devices each configured to issue said transactions.

13. The apparatus according to claim 1, comprising an interconnect to maintain coherency between the master device and at least one other master device or cache, wherein the interconnect comprises the processing unit.

14. The apparatus according to claim 1, comprising a memory controller to control access to a memory, wherein the memory controller comprises the processing unit.

15. A master device comprising:

transaction issuing circuitry to issue a transactions specifying a target address and comprising a data field for transporting at least one operand value;

wherein the transaction issuing circuitry is configured to issue a compare-and-swap transaction for which said at least one operand value comprises a compare data value and a swap data value, the compare-and-swap transaction for controlling a processing unit to select whether to write the swap data value to a storage location corresponding to the target address in dependence on whether the compare data value matches a target data value read from the storage location, an offset portion of the target address indicating the position of the target data value within the storage location;

wherein when issuing the compare-and-swap transaction, the transaction issuing circuitry is configured to pack the compare data value into a first region of said data field selected in dependence on said offset portion of the target address and having a position within said data field corresponding to the position of the target data value within the storage location.

16. A processing unit comprising:

transaction receiving circuitry to receive a transactions specifying a target address and comprising a data field for transporting at least one operand value, wherein the transaction receiving circuitry is configured to receive a compare-and-swap transaction for which said at least one operand value comprises a compare data value and a swap data value;

data access circuitry responsive to the compare-and-swap transaction to read a storage location corresponding to the target address, an offset portion of the target address indicating the position of a target data value within the storage location; and

processing circuitry responsive to the compare-and-swap transaction to select whether the data access circuitry is to write the swap data value to said storage location in dependence on whether the compare data value matches the target data value;

wherein the processing circuitry is configured to locate the compare data value within a first region of said data field selected in dependence on said offset portion of the target address and having a position within said data field corresponding to the position of the target data value within the storage location.

17. A data processing method comprising:

issuing a compare-and-swap transaction specifying a target address and comprising a data field for transporting a compare data value and a swap data value; and

in response to the compare-and-swap transaction, selecting whether to write the swap data value to a storage location corresponding to the target address in dependence on whether the compare data value matches a target data value read from the storage location, an offset portion of the target address indicating the position of the target data value within the storage location;

wherein in the compare-and-swap transaction, the compare data value is packed into a first region of said data field selected in dependence on said offset portion of the target address and having a position within said data field corresponding to the position of the target data value within the storage location.