Method and system for accessing a flash memory device

• US 10,223,003 B2
• Filed: 11/09/2017
• Issued: 03/05/2019
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US15/807,720
• Publication Number:
  US 20180129427A1
• Time in Patent Office: 481 Days
• Field of Search: 36518511, 36518533, 36518904, 36523003, 36523009
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A flash memory device comprising:

a plurality of flash memory blocks;

a clock input configured to receive a clock signal;

a chip select input configured to receive a chip select signal;

a plurality of serial data interfaces, each serial data interface configured to transfer a plurality of data streams in synchronization with the clock signal only when the chip select signal is in an active state; and

control circuitry configured to;

perform a program operation in response to a first data stream, the first data stream comprising a program command, a first address and write data, the write data configured to be programmed to a first flash memory block of the plurality of flash memory blocks and addressed by the first address,

perform a read operation in response to a second data stream, the second data stream comprising a read command and a second address, the read operation configured to retrieve read data from a second flash memory block of the plurality of flash memory blocks and addressed by the second address, and

transfer the read data as a third data stream before completing the program operation on the first flash memory block; and

a status indicator configured to indicate whether the program operation is in progress.

2. The flash memory device of claim 1, further comprising a second status indicator configured to indicate whether the read operation is in progress.

3. The flash memory device of claim 1, further comprising an error correcting circuit (ECC) configured to correct an error in the read data if the error is detected.

4. The flash memory device of claim 1, wherein the control circuitry comprises an addressing circuitry configured to parse a data stream to extract a location of a flash memory block of the plurality of flash memory blocks.

5. The flash memory device of claim 1, further comprising an input buffer configured to receive the plurality of data streams, the input buffer enabled only when the chip select signal is in the active state.

6. The flash memory device of claim 1, further comprising a temporary register configured to temporarily store the write data of the first data stream.

7. The flash memory device of claim 1, further comprising a serial-to-parallel register configured to convert a serial data to a parallel data.

8. The flash memory device of claim 1, further comprising a parallel-to-serial register configured to convert a parallel data to a serial data.

9. The flash memory device of claim 1, wherein the clock signal is a free running clock signal.

10. The flash memory device of claim 1, wherein each flash memory block comprises a plurality of NAND-type flash memory cells.

11. The flash memory device of claim 1, wherein each flash memory block comprises a plurality of NOR-type flash memory cells.

12. The flash memory device of claim 1, wherein the status indicator is comprised in a status register.