Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration

• US 10,223,009 B2
• Filed: 10/26/2016
• Issued: 03/05/2019
• Est. Priority Date: 10/20/2016
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Inventors: Simionescu, Horia, Hoglund, Timothy, Veerla, Sridhar Rao, Pandit, Panthini, Radhakrishnan, Gowrisankar
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US15/335,037
• Publication Number:
  US 20180113634A1
• Time in Patent Office: 860 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A system and method for efficient cache buffering are provided. The disclosed method includes receiving an Input/Output (I/O) command from a host system at a storage controller, parsing the I/O command at the storage controller with a host I/O manager to extract command instructions therefrom. The host I/O manager is able to generate at least one local message that includes the command instructions extracted from the I/O command and transmit the at least one local message to a cache manager. The cache manager is enabled to work in local memory to execute the command instructions contained in the at least one message. The cache manager is also configured to chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system.

Claims

1. A method of managing cache buffering, the method comprising:

receiving an Input/Output (I/O) command from a host system at a storage controller, the I/O command requiring one or more blocks of memory from a cache memory;

parsing the I/O command at the storage controller with a host I/O manager to extract command instructions therefrom;

generating, at the host I/O manager, at least one local message that includes the command instructions extracted from the I/O command;

transmitting the at least one local message to a cache manager; and

enabling the cache manager to work in local memory to execute the command instructions contained in the at least one message, wherein the cache manager is configured to chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system, wherein each buffer segment is represented by a corresponding extent, and wherein the cache manager groups extents as extents are created so as to have at least two extents sharing a single frame.

2. The method of claim 1, wherein at least some buffer segments in the chain of multiple buffer segments belong to a common extent and are aligned and contiguous buffer segments.

3. The method of claim 2, wherein the common extent comprises at least sixteen aligned and contiguous buffer segments.

4. The method of claim 2, wherein the cache manager groups extents two-by-two as extents are created.

5. The method of claim 4, wherein the cache manager updates two nibbles of a cache frame anchor to indicate which two extents among a plurality of extents share a frame that is referenced in an extent frame identification field in the cache frame anchor.

6. The method of claim 5, wherein the cache frame anchor comprises an extents section and a buffer section and wherein the extents section comprises the extent frame identification field and the two nibbles and wherein the buffer section comprises a plurality of buffer segments belonging to a particular extent that is referenced in the extents section.

7. The method of claim 6, wherein the cache frame anchor comprises a hash section, a dirty list section, and an identity section that enable the cache frame anchor to represent the variable stripe sizes.

8. The method of claim 1, wherein the cache manager is executed by the storage controller.

9. The method of claim 1, wherein the I/O command comprises at least one of a read command and a write command and wherein the at least one local message comprises a Local Message Identifier (LMID) that is used to refer to an identifier of a local message frame.

10. A storage system, comprising:

a controller comprising a processor and memory having instructions stored thereon that are executable by the processor, the instructions including;

a host Input/Output (I/O) manager that receives I/O commands from a host system and generates a corresponding local message for distribution within the controller; and

a cache manager that is configured to work in local memory to execute command instructions contained in local messages received from the host I/O manager and, in response thereto, chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system, wherein each buffer segment is represented by a corresponding extent, and wherein the cache manager groups extents as extents are created so as to have at least two extents sharing a single frame.

11. The system of claim 10, wherein at least some buffer segments in the chain of multiple buffer segments belong to a common extent and are aligned and contiguous buffer segments.

12. The system of claim 11, wherein the common extent comprises at least sixteen aligned and contiguous buffer segments.

13. The system of claim 11, wherein the cache manager groups extents two-by-two as extents are created.

14. The system of claim 13, wherein the cache manager updates two nibbles of a cache frame anchor to indicate which two extents among a plurality of extents share a frame that is referenced in an extent frame identification field in the cache frame anchor.

15. The system of claim 14, wherein the cache frame anchor comprises an extents section and a buffer section and wherein the extents section comprises the extent frame identification field and the two nibbles and wherein the buffer section comprises a plurality of buffer segments belonging to a particular extent that is referenced in the extents section.

16. The system of claim 15, wherein the cache frame anchor comprises a hash section, a dirty list section, and an identity section that enable the cache frame anchor to represent the variable stripe sizes.

17. The controller of claim 15, wherein the cache frame anchor comprises an extents section and a buffer section and wherein the extents section comprises the extent frame identification field and the two nibbles and wherein the buffer section comprises a plurality of buffer segments belonging to a particular extent that is referenced in the extents section.

18. A controller situated between a host system and a data storage array, the controller comprising:

a processor; and

memory coupled to the processor, the memory including instructions that, when executed by the processor, enable the controller to perform the following;

receive an Input/Output (I/O) command from the host system, the I/O command requiring one or more blocks of memory from a cache memory;

parse the I/O command to extract command instructions therefrom;

generate at least one local message that includes the command instructions extracted from the I/O command;

transmit the at least one local message; and

chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system, wherein each buffer segment is represented by a corresponding extent, and wherein as extents are created extents are grouped so as to have at least two extents sharing a single frame.

19. The controller of claim 18, wherein at least some buffer segments in the chain of multiple buffer segments belong to a common extent and are aligned and contiguous buffer segments and wherein the extents are grouped two-by-two as extents are created.

20. The controller of claim 19, wherein the controller is further enables to update two nibbles of a cache frame anchor to indicate which two extents among a plurality of extents share a frame that is referenced in an extent frame identification field in the cache frame anchor.