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System and method for implementing super word line zones in a memory device

  • US 10,223,022 B2
  • Filed: 01/27/2017
  • Issued: 03/05/2019
  • Est. Priority Date: 01/27/2017
  • Status: Active Grant
First Claim
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1. A data storage system comprising a memory controller that controls operation of a plurality of memory access units, wherein the memory controller is configured to perform steps of:

  • classifying each block within the plurality of memory access units into good blocks, partially bad blocks, and bad blocks, wherein the good blocks include only good word line zones, each of the partially bad blocks includes at least one, and not more than N, bad word line zones, and each of the bad blocks including more than N bad word line zones, wherein N is a positive integer; and

    constructing a set of superblocks employing the good blocks and the partially bad blocks, wherein;

    the memory controller is configured to construct a set of super word line zones within each superblock in the set of superblocks, wherein each block within the superblock contributes a good word line zone to each super word line zone within a predominant subset of the set of super word line zones;

    the memory controller is configured to determine whether to modify super word line zones within the superblock or to initiate garbage collection upon encounter of a program error at the superblock; and

    upon encounter of the program error during execution of a program at the superblock, the memory controller is configured to;

    determine a total number of operational partially bad blocks that have at least one, and not more than (N+P), bad word line zones within the superblock, wherein P is a first non-negative integer; and

    determine whether the total number of operational partially bad blocks exceeds M+Q, wherein M is a maximum number M for a total number of partially bad blocks in any single superblock during construction of the set of superblocks, and Q is a second non-negative integer, andwherein each of the plurality of memory access units comprises a single NAND or NOR flash memory integrated circuit die, a plurality of NAND or NOR flash memory integrated circuit dies, or a plane of a NAND or NOR flash memory integrated circuit die containing multiple planes.

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