System and method for implementing super word line zones in a memory device
First Claim
1. A data storage system comprising a memory controller that controls operation of a plurality of memory access units, wherein the memory controller is configured to perform steps of:
- classifying each block within the plurality of memory access units into good blocks, partially bad blocks, and bad blocks, wherein the good blocks include only good word line zones, each of the partially bad blocks includes at least one, and not more than N, bad word line zones, and each of the bad blocks including more than N bad word line zones, wherein N is a positive integer; and
constructing a set of superblocks employing the good blocks and the partially bad blocks, wherein;
the memory controller is configured to construct a set of super word line zones within each superblock in the set of superblocks, wherein each block within the superblock contributes a good word line zone to each super word line zone within a predominant subset of the set of super word line zones;
the memory controller is configured to determine whether to modify super word line zones within the superblock or to initiate garbage collection upon encounter of a program error at the superblock; and
upon encounter of the program error during execution of a program at the superblock, the memory controller is configured to;
determine a total number of operational partially bad blocks that have at least one, and not more than (N+P), bad word line zones within the superblock, wherein P is a first non-negative integer; and
determine whether the total number of operational partially bad blocks exceeds M+Q, wherein M is a maximum number M for a total number of partially bad blocks in any single superblock during construction of the set of superblocks, and Q is a second non-negative integer, andwherein each of the plurality of memory access units comprises a single NAND or NOR flash memory integrated circuit die, a plurality of NAND or NOR flash memory integrated circuit dies, or a plane of a NAND or NOR flash memory integrated circuit die containing multiple planes.
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Accused Products
Abstract
A set of superblocks can be constructed by a memory controller employing good blocks and partially bad blocks in a plurality of memory access units. Each functional memory access unit among the plurality of memory access units contributes a single block that is a good block or a partially bad block to each superblock. The memory controller can further construct a set of super word line zones within each superblock in the set of superblocks. Each block within a superblock contributes a good word line zone to each super word line zone. Upon encounter of a program error at run time, the super word line zones within the superblock may be modified to continue running the program employing modified super word line zones for the superblock.
15 Citations
5 Claims
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1. A data storage system comprising a memory controller that controls operation of a plurality of memory access units, wherein the memory controller is configured to perform steps of:
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classifying each block within the plurality of memory access units into good blocks, partially bad blocks, and bad blocks, wherein the good blocks include only good word line zones, each of the partially bad blocks includes at least one, and not more than N, bad word line zones, and each of the bad blocks including more than N bad word line zones, wherein N is a positive integer; and constructing a set of superblocks employing the good blocks and the partially bad blocks, wherein; the memory controller is configured to construct a set of super word line zones within each superblock in the set of superblocks, wherein each block within the superblock contributes a good word line zone to each super word line zone within a predominant subset of the set of super word line zones; the memory controller is configured to determine whether to modify super word line zones within the superblock or to initiate garbage collection upon encounter of a program error at the superblock; and upon encounter of the program error during execution of a program at the superblock, the memory controller is configured to; determine a total number of operational partially bad blocks that have at least one, and not more than (N+P), bad word line zones within the superblock, wherein P is a first non-negative integer; and determine whether the total number of operational partially bad blocks exceeds M+Q, wherein M is a maximum number M for a total number of partially bad blocks in any single superblock during construction of the set of superblocks, and Q is a second non-negative integer, and wherein each of the plurality of memory access units comprises a single NAND or NOR flash memory integrated circuit die, a plurality of NAND or NOR flash memory integrated circuit dies, or a plane of a NAND or NOR flash memory integrated circuit die containing multiple planes. - View Dependent Claims (2, 3)
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4. A method of operating a data storage system comprising a memory controller that controls operation of a plurality of memory access units, wherein each of the plurality of memory access units comprises a single NAND or NOR flash memory integrated circuit die, a plurality of NAND or NOR flash memory integrated circuit dies, or a plane of a NAND or NOR flash memory integrated circuit die containing multiple planes, the method comprising steps of:
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classifying, by employing the memory controller, each block within the plurality of memory access units into good blocks, partially bad blocks, and bad blocks, wherein good blocks include only good word line zones, each of the partially bad blocks includes at least one, and not more than N, bad word line zones, and each of the bad blocks including more than N bad word line zones, wherein N is a positive integer; constructing, by employing the memory controller, a set of superblocks employing the good blocks and the partially bad blocks; constructing, by employing the memory controller, a set of super word line zones within each superblock in the set of superblocks, wherein each block within the superblock contributes a good word line zone to each super word line zone within a predominant subset of the set of super word line zones; determining, by employing the memory controller, whether to modify super word line zones within the superblock or to initiate garbage collection upon encounter of a program error at the superblock; and performing, upon encounter of the program error during execution of a program at the superblock, a set of steps comprising; a first step of determining, by employing the memory controller, a total number of operational partially bad blocks that have at least one, and not more than (N+P), bad word line zones within the superblock, wherein P is a first non-negative integer; and a second step of determining, by employing the memory controller, whether the total number of operational partially bad blocks exceeds M+Q, wherein M is a maximum number M for a total number of partially bad blocks in any single superblock during construction of the set of superblocks, and Q is a second non-negative integer. - View Dependent Claims (5)
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Specification