Storage device, semiconductor device, electronic device, and server system
First Claim
1. A storage device comprising:
- a first memory cell and a second memory cell;
a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line;
a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line; and
an analog-digital converter circuit,wherein the digital-analog converter circuit is configured to apply voltages as first signals to the first memory cell and the second memory cell,wherein the sense circuit is configured to select as a second signal a higher one of the voltages applied to the first memory cell and the second memory cell, andwherein the analog-digital converter circuit is configured to convert the second signal into a digital signal.
1 Assignment
0 Petitions
Accused Products
Abstract
Data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit. The digital-analog converter circuit has a function of applying voltages as first signals to the first memory cell and the second memory cell. Even when a soft error occurs in the first memory cell or the second memory cell, the storage device has a function of recovering data corrupted by the soft error because the sense circuit selects and outputs a higher one of the voltages applied to the first memory cell and the second memory cell.
28 Citations
19 Claims
-
1. A storage device comprising:
-
a first memory cell and a second memory cell; a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line; a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line; and an analog-digital converter circuit, wherein the digital-analog converter circuit is configured to apply voltages as first signals to the first memory cell and the second memory cell, wherein the sense circuit is configured to select as a second signal a higher one of the voltages applied to the first memory cell and the second memory cell, and wherein the analog-digital converter circuit is configured to convert the second signal into a digital signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A storage device comprising:
-
a first memory cell and a second memory cell; a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line; a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line; and an analog-digital converter circuit, wherein the digital-analog converter circuit is configured to apply voltages as first signals to the first memory cell and the second memory cell, wherein the sense circuit is configured to select as a second signal a higher one of the voltages applied to the first memory cell and the second memory cell, wherein the analog-digital converter circuit is configured to convert the second signal into a digital signal, wherein each of the first memory cell and the second memory cell comprises a transistor comprising a semiconductor layer, and wherein the transistor of the second memory cell is provided over the transistor of the first memory cell with an insulating layer therebetween. - View Dependent Claims (12, 13, 14)
-
-
15. A storage device comprising:
-
a first memory cell and a second memory cell; a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line; a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line; and an analog-digital converter circuit, wherein the digital-analog converter circuit is configured to apply voltages as first signals to the first memory cell and the second memory cell, wherein the sense circuit is configured to select as a second signal a higher one of the voltages applied to the first memory cell and the second memory cell, wherein the analog-digital converter circuit is configured to convert the second signal into a digital signal, wherein each of the first memory cell, the second memory cell, and the sense circuit comprises a transistor, wherein the transistor of the first memory cell is provided over the transistor of the sense circuit with a first insulating layer therebetween, and wherein the transistor of the second memory cell is provided over the transistor of the first memory cell with a second insulating layer therebetween. - View Dependent Claims (16, 17, 18, 19)
-
Specification