High capacity memory system with improved command-address and chip-select signaling mode

• US 10,223,299 B2
• Filed: 12/18/2014
• Issued: 03/05/2019
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Abhyankar, Abhijit, Rajan, Suresh
• Primary Examiner(s): Nam, Hyun
• Application Number:
  US15/101,870
• Publication Number:
  US 20160314085A1
• Time in Patent Office: 1,538 Days
• Field of Search: None
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory controller and buffers on memory modules each operate in two modes, depending on the type of mother-board through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

Claims

1. A buffer device for operation on a memory module, the buffer device comprising:

a chip select (CS) decoder; and

a modal register to store a value indicative of one of at least two modes of operation, wherein,

in a first mode of operation, the buffer device drives a chip select signal group received on a primary-side CS interface onto a corresponding secondary-side CS interface;

in a second mode of operation, the CS decoder decodes a CS signal group received on the primary-side CS interface to create signals for the secondary-side CS interface;

in the first mode of operation, the buffer device drives an on-die termination (ODT) signal received on a primary-side ODT line onto a corresponding secondary ODT line; and

in the second mode, the buffer device, based at least in part on an output of the CS decoder, generates an ODT signal to transmit on the secondary ODT line.

2. The buffer device of claim 1, wherein,

in the first mode of operation, the buffer device drives a clock enable (CKE) signal received on a primary CKE line onto a corresponding secondary CKE line;

and

in the second mode of operation, the buffer device, based at least in part on an output of the CS decoder, generates a CKE signal to transmit on a secondary CKE line.

3. The buffer device of claim 1, comprising a plurality of physical interface connections, and wherein the primary-side CS interface uses different sets of the physical interface connections in the first and second modes of operation.

4. The buffer device of claim 1, wherein the buffer device comprises a registering clock driver integrated circuit and a plurality of data buffer integrated circuits, each of which comprises at least a partial CS decoder and performs at least a portion of the CS signal group decoding in the second mode of operation.

5. A buffer device for operation on a multi-rank, multi-device-site-per-rank memory module, the buffer device comprising:

a chip select (CS) decoder; and

a secondary-side CS interface having multiple CS signal outputs for each memory module rank, the buffer device capable of using the CS signal outputs to independently select different subgroups of device sites that are each less than a half rank of device sites, and wherein,

in a first mode, the buffer device receives a chip select (CS) signal group, and asserts multiple corresponding ones of the multiple CS signal outputs on the secondary-side CS interface to select multiple subgroups of device sites to provide a corresponding full rank selection; and

in a second mode, the buffer device receives a fully encoded CS signal group, the CS decoder decodes the encoded CS signal group to determine one or more of the subgroups of device sites to select, and the buffer device asserts at least one of the multiple CS signal outputs on the secondary-side CS interface to provide a corresponding partial rank selection.

6. The buffer device of claim 5, wherein,

in at least the second mode, the fully encoded CS signal group contains CS information that applies to more than one slot in a multiple-slot memory system.

7. The buffer device of claim 5, wherein the buffer device comprises a registering clock driver integrated circuit and a plurality of data buffer integrated circuits, each of which comprises at least a partial CS decoder and performs at least a portion of the CS signal group decoding in the second mode.

8. The buffer device of claim 7, wherein the registering clock driver integrated circuit receives the fully encoded CS signal group and retransmits at least a portion of the fully encoded CS signal group to each of the data buffer integrated circuits.

9. The buffer device of claim 8, wherein each of the data buffers is paired with multiple ones of the device sites, and generates, for the paired device sites, the CS signal outputs that select those device sites.

10. The buffer device of claim 5, wherein,

in the first mode, the buffer device receives a point-to-point on-die termination (ODT) signal and drives a corresponding secondary-side ODT signal;

and

in the second mode, the memory module does not receive an explicit ODT signal, and drives a secondary-side ODT signal based at least in part on an output of the CS decoder.

11. The buffer device of claim 5, wherein the memory module is capable of use in a multi-slot memory channel, the buffer device further comprising a first register that is programmable to contain a module total related to a number of memory channel slots that are populated, the CS decoder using the module total in a determination of which of the subgroups of devices to select for different values of the encoded CS signal group.

12. The buffer device of claim 11, the buffer device further comprising a second register that is programmable to contain a slot ID identifying the memory channel slot to which the memory module connects, the CS decoder using the slot ID in the determination of which of the subgroups of devices to select for different values of the encoded CS signal group.

13. The buffer device of claim 11, wherein in the first mode the module total is 1.

14. The buffer device of claim 5, wherein in the first mode the received CS signal group comprises at least one decoded chip select.

15. The buffer device of claim 5, wherein, in a third mode, the buffer device receives a CS signal group and, at least when the CS signal group identifies a rank assertion, the buffer device communicates CS signal group information to a buffer device on another module.

16. An apparatus comprising:

a memory controller comprising a modal register to store a value indicative of at least two modes of operation, wherein,

in a first mode, the controller asserts a first decoded chip select (CS) output to select multiple subgroups of device sites on one of a plurality of memory modules to provide a corresponding full rank selection; and

in a second mode, the controller drives a fully encoded CS signal group output to each of the plurality of memory modules, the fully encoded CS signal group output identifying one or more of the subgroups of device sites to select to provide a corresponding partial rank selection.

17. The apparatus of claim 16, the memory controller comprising multiple output groups that can each function as a CS signal group output in the second mode, the memory controller in the second mode driving the same fully encoded CS signal group output on each of the output groups.

18. The apparatus of claim 17, wherein the multiple output groups also can each function as a command address (CA) signal group output in the second mode, the CS signal group outputs transmitted as part of the CA signal group output, the memory controller in the second mode driving the same CA signal group output on each of the output groups.

19. The apparatus of claim 18, wherein in the first mode the memory controller transmits a single CA signal group, not including the first decoded CS output, on a wider group output that includes outputs from at least two of the multiple output groups.